mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 194

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Bit Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Table 170 - Counter Indication and Counter Overflow Latched Status Register (Address Y25) (E1)
CEOL CRC-4 Error Counter Overflow Latch. When the CRC-4 Error Counter (CEC15-0 register
PCOL PRBS CRC-4 Counter Overflow Latch. When the PRBS CRC-4 Counter (PCC7-0 register
FEOL Frame Alignment Signal (FAS) Error Counter Overflow Latch. When the FAS Error Counter
BEOL Frame Alignment Signal (FAS) Bit Error Counter Overflow Latch. When the FAS Bit Error
VEOL Bipolar Violation (BPV) Error Counter Overflow Latch. When the BPV Error Counter (VEC15-0
EEOL E-Bit Error Counter Overflow Latch. When the E-Bit Error Counter (EEC15-0 register address
SLOL Loss of Sync Counter Overflow Latch. When the Loss of Sync Counter (SLC15-0 register
CEIL
FEIL
BEIL
VEIL
EEIL
#
#
not used.
address Y16) overflows (3FF to 00), this status bit is latched to one. This bit is cleared when either
this register, or the interrupt status register (register address Y35) is read.
(FEC7-0 register address Y1A lower byte) overflows (FF to 00), this status bit is latched to one.
This bit is cleared when either this register, or the interrupt status register (register address Y35) is
read.
Frame Alignment Signal (FAS) Error Counter Indication Latch. When the FAS Error Counter
(FEC7-0 register address Y1A lower byte) is incremented by one, this status bit is latched to one.
This bit is cleared when either this register or the interrupt status register (register address Y35) is
read.
Counter (BEC7-0 register address Y1A upper byte) overflows (FF to 00), this status bit is latched to
one. This bit is cleared when either this register, or the interrupt status register (register address
Y35) is read.
Frame Alignment Signal (FAS) Bit Error Counter Indication Latch. When the FAS Bit Error
Counter (BEC7-0 register address Y1A upper byte) is incremented by one, this status bit is latched
to one. This bit is cleared when either this register, or the interrupt status register (register address
Y35) is read.
address Y19) overflows (3FF to 000), this status bit is latched to one. This bit is cleared when either
this register, or the interrupt status register (register address Y35) is read.
CRC-4 Error Counter Indication Latch. When the CRC-4 Error Counter (CEC15-0 register
address Y19) is incremented by one, this status bit is latched to one. This bit is cleared when either
this register, or the interrupt status register (register address Y35) is read.
register address Y18) overflows (FFFF to 000), this status bit is latched to one. This bit is cleared
when either this register, or the interrupt status register (register address Y35) is read.
Bipolar Violation (BPV) Error Counter Indication Latch. When the BPV Error Counter (VEC15-0
register address Y18) is incremented by one, this status bit is latched to one. This bit is cleared
when either this register, or the interrupt status register (register address Y35) is read.
Y17) overflows (3FF to 000), this status bit is latched to one. This bit is cleared when either this
register, or the interrupt status register (register address Y35) is read.
E-Bit Error Counter Indication Latch. When the E-Bit Error Counter (EEC15-0 register address
Y17) is incremented by one, this status bit is latched to one. This bit is cleared when either this
register, or the interrupt status register (register address Y35) is read.
address Y15 lower byte) overflows (FF to 00), this status bit is latched to one. This bit is cleared
when either this register, or the interrupt status register (register address Y35) is read.
not used.
Zarlink Semiconductor Inc.
MT9072
Functional Description
194
Data Sheet