mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 196

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

15-4
Bit
Bit
4
3
2
1
0
3
2
1
0
Table 171 - CAS, National, CRC-4 Local and Timer Latched Status Register (Address Y26) (E1)
ONESECL One Second Timer Status Latch. When the ONESEC status bit (register address Y11)
CASRL
CALNL
BSYNCP
Name
LOSSP
T2L
T1L
Name
RAIP
AISP
Table 172 - Performance Persistent Latched Status Register (Address Y27) (E1)
#
Receive Channel Associated Signaling (CAS) Change Latch. When any of the receive
CAS (i.e., ABCD) bits in the Receive CAS Data Registers (address Y70-Y8F) change state,
this status bit is latched to one. This bit is set on a basic frame (FPi) basis. This bit is cleared
when either this register, or the corresponding interrupt status register (register address Y34)
is read.
CRC-4 Alignment 2 ms Timer Latch. When the CALN status bit (register address Y11)
toggles from zero to one, this status bit is latched to one. This bit is set on a 2 ms or CRC-4
multiframe frame basis. This bit is cleared when either this register, or the corresponding
interrupt status register (register address Y36) is read.
Timer 2 Latch. When the CRC-4 T2 (10ms) status bit (register address Y11) toggles from
zero to one, this status bit is latched to one. This bit is set on a basic frame (FPi) basis. This
bit is cleared when either this register, or the corresponding interrupt status register (register
address Y36) is read.
Timer 1 Latch. When the CRC-4 T1 (100ms) status bit (register address Y11) toggles from
zero to one, this status bit is latched to one. This bit is set on a basic frame (FPi) basis. This
bit is cleared when either this register, or the corresponding interrupt status register (register
address Y36) is read.
toggles from zero to one, this status bit is latched to one. This bit is set on a basic frame (FPi)
basis. This bit is cleared when either this register, or the corresponding interrupt status
register (register address Y36) is read.
not used.
Remote Alarm Indication Status Persistent Latch. When the RAI (A) status bit (register
address Y12 and Y13) toggles from zero to one, this status bit is latched to one. This bit is
cleared when this register is read while the RAI status bit is zero.
Alarm Indication Status Signal Persistent. When the AIS status bit (register address
Y12) toggles from zero to one, this status bit is latched to one. This bit is cleared when this
register is read while the AIS status bit is zero.
Loss of Signal Status Indication Persistent Latch. When the LOSS status bit (register
address Y12) toggles from zero to one, this status bit is latched to one. This bit is cleared
when this register is read while the LOSS status bit is zero.
Receive Basic Frame Alignment Persistent Latch. When the BSYNC status bit (register
address Y10) toggles from zero to one, this status bit is latched to one. This bit is cleared
when this register is read while the BSYNC status bit is zero.
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MT9072
Functional Description
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Functional Description
Data Sheet