mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 20

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Table 147 - CAS Control and Data Register (R/W Address Y05) (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 148 - HDLC & CCS ST-BUS Control Register (R/W Address Y06) (E1). . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 149 - CCS to ST-BUS CSTi and CSTo Map Control Register (R/W Address Y07) (E1) . . . . . . . . . . . . . . 179
Table 150 - DataLink Control Register (R/W Address Y08) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 151 - Receive Idle Code Register(Y09) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 152 - Transmit Idle Code Register(Y0A) (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 153 - Synchronization & CRC-4 Remote Status (R Address Y10) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 154 - CRC-4 Timers & CRC-4 Local Status (R Address Y11) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 155 - Alarms & Multiframe Signaling (MAS) Status (R Address Y12) (E1). . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 156 - Non-Frame Alignment (NFAS) Signal and Frame Alignment Signal (FAS) Status
Table 157 - Phase Indicator Status (R Address Y14) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 158 - PRBS Error Counter & PRBS CRC-4 Counter (R/W Address Y15) (E1) . . . . . . . . . . . . . . . . . . . . . 187
Table 159 - Loss of Basic Frame Synchronization Counter with Auto Clear (R/W Address Y16) (E1) . . . . . . . . 188
Table 160 - E-bit Error Counter (R/W Address Y17) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 161 - Bipolar Violation (BPV) Error Counter (R/W Address Y18) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 162 - CRC-4 Error Counter (R/W Address Y19) (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 163 - Frame Alignment Signal (FAS) Bit Error Counter & FAS Error Counter (R/W Address Y1A) (E1) . . 190
Table 164 - Transmit Byte Counter Position and HDLC Test Status(Y1C) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 165 - HDLC Status Register(Y1D) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 166 - HDLC Receive CRC(Y1E) (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 167 - HDLC Receive FIFO(Y1F) (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 168 - HDLC Status Latch(Y23) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 169 - Sync, CRC-4 Remote, Alarms, MAS and Phase Latched Status Register (Address Y24) (E1) . . . . 192
Table 170 - Counter Indication and Counter Overflow Latched Status Register (Address Y25) (E1) . . . . . . . . . 194
Table 171 - CAS, National, CRC-4 Local and Timer Latched Status Register (Address Y26) (E1) . . . . . . . . . . . 195
Table 172 - Performance Persistent Latched Status Register (Address Y27) (E1) . . . . . . . . . . . . . . . . . . . . . . . 196
Table 173 - E-Bit Error Count Latch (R Address Y28) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 174 - Bipolar Violation (BPV) Error Count Latch (R/W Address Y29) (E1). . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 175 - CRC-4 Error Count Latch (R/W Address Y2A) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 176 - Frame Alignment Signal (FAS) Error Count Latch (R/W Address Y2B) (E1) . . . . . . . . . . . . . . . . . . 198
Table 177 - HDLC Interrupt Status Register(Y33) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 178 - Sync, CRC-4 Remote, Alarms, MAS and Phase Interrupt Status Register (Address Y34) (E1) . . . . 200
Table 179 - Counter Indication and Counter Overflow Interrupt Status Register (Address Y35) (E1) . . . . . . . . . 201
Table 180 - CAS, National, CRC-4 Local and Timer Interrupt Status Register (Address Y36) (E1) . . . . . . . . . . 203
Table 181 - HDLC Interrupt Mask Register (Address Y43) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 182 - Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Mask Register (Address Y44) (E1) . .
Table 183 - Counter (Counter Indication and Counter Overflow) Interrupt Mask Register (Address Y45) (E1). . 207
Table 184 - National (CAS, National, CRC-4 Local and Timers) Interrupt Mask Register (Address Y46) (E1) . . 209
Table 185 - Channel n, Transmit CAS Data Register (Address Y51-Y6F) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 186 - Channel n, Receive CAS Data Register (Address Y71-Y8F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 187 - Timeslot (TS) n (n = 0 to 31) Control Register (Address Y90 (TS0) to YAF(TS31)) (E1) . . . . . . . . . 211
Table 188 - Transmit National Bits (Sa4 - Sa8) TNn (n = 0 to 4) Data Register
Table 189 - Receive National Bits (Sa4 - Sa8) RNn
Table 190 - HDLC Control1(YF2) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 191 - HDLC Test Control(YF3) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
(R Address Y13) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
205
(R/W Address YB0 to YB4) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
(n = 0 to 4) Data Register (R/W Address YC0 to YC4) (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Zarlink Semiconductor Inc.
List of Tables
MT9072
20
Data Sheet