mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 201

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Table 178 - Sync, CRC-4 Remote, Alarms, MAS and Phase Interrupt Status Register (Address Y34) (E1)
Bit
Bit
15
14
13
12
11
4
3
2
1
0
Table 179 - Counter Indication and Counter Overflow Interrupt Status Register (Address Y35) (E1)
MSYNCI
CSYNCI
BSYNCI
RFAILI
CEFSI
Name
Name
BEOI
SLOI
FEOI
FEII
#
Consecutively Errored Frame Alignment Signal Interrupt. This bit is one when the
corresponding latched status bit (CEFSL, register address Y24) is set, and the corresponding
mask bit is unmasked (CEFSM, register address Y44). This bit is cleared when either this
register, or the latched status register is read.
Remote CRC-4 Multiframe Generator/Detector Failure Interrupt. This bit is one when the
corresponding latched status bit (RFAILL, register address Y24) is set, and the corresponding
mask bit is unmasked (RFAILM, register address Y44). This bit is cleared when either this
register, or the latched status register is read.
Receive CRC-4 Synchronization Interrupt. This bit is one when the corresponding latched
status bit (CSYNCL, register address Y24) is set, and the corresponding mask bit is
unmasked (CSYNCM, register address Y44). This bit is cleared when either this register, or
the latched status register is read.
Receive Multiframe Alignment Interrupt. This bit is one when the corresponding latched
status bit (MSYNCL, register address Y24) is set, and the corresponding mask bit is
unmasked (MSYNCM, register address Y44). This bit is cleared when either this register, or
the latched status register is read.
Receive Basic Frame Alignment Interrupt. This bit is one when the corresponding latched
status bit (BSYNCL, register address Y24) is set, and the corresponding mask bit is
unmasked (BSYNCM, register address Y44). This bit is cleared when either this register, or
the latched status register is read.
not used.
Loss of Sync Counter Overflow Interrupt. This bit is one when the corresponding latched
status bit (SLOL, register address Y25) is set, and the corresponding mask bit is unmasked
(SLOM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
Frame Alignment Signal (FAS) Error Counter Overflow Interrupt. This bit is one when the
corresponding latched status bit (FEOL, register address Y25) is set, and the corresponding
mask bit is unmasked (FEOM, register address Y45). This bit is cleared when either this
register, or the latched status register is read.
Frame Alignment Signal (FAS) Error Counter Indication Interrupt. This bit is one when
the corresponding latched status bit (FEIL, register address Y25) is set, and the
corresponding mask bit is unmasked (FEIM, register address Y45). This bit is cleared when
either this register, or the latched status register is read.
Frame Alignment Signal (FAS) Bit Error Counter Overflow Interrupt. This bit is one when
the corresponding latched status bit (BEOL, register address Y25) is set, and the
corresponding mask bit is unmasked (BEOM, register address Y45). This bit is cleared when
either this register, or the latched status register is read.
Zarlink Semiconductor Inc.
MT9072
Functional Description
Functional Description
201
Data Sheet