mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 216

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

17.2.14
The Global Control and Status Registers are common to the T1 and E1 operation. The global registers are
accessed by address hex 9xx ( A
13-5
3-1
Bit
15
14
15-8
7 - 0
4
0
Bit
15-8
7 - 0
Bit
STBUS
Name
RSTC
T1E0
CK1
(1)
(0)
(0)
#
#
Global Control and Status Registers(900-91F) Bit Functions
(00000000)
CNT7-0
(00000000)
Name
BIT7-0
Name
#
T1E0. This bit determines if the chip will operate in T1 or E1 mode for all 8 framers. If the value
of this bit is changed the chip is reset in E1 or T1 default register mode. If the bit is set to 1, all
the framer register values are set to T1 defaults. For a setting of 0 the register values are set to
E1 defaults. This action takes approximately 34 1.5444 clock cycles. Hence any writes to
registers should be done on the next 125 usec frame after setting or clearing this bit.
ST-BUS Enable. If zero, ST-BUS timing is enabled. If one, GCI timing is enabled (only available
for 2.048 Mb/s mode). See Figures 24-31.
not used
Clock Rate. These clock select bits determine the system clock at the CKi pin and the receive
frame pulse at the FPi pin as follows (See Figures 24 to 31):
CK1
0
1
not used.
Common Reset. When this bit is changed from zero to one, all eight framers will reset to their
default T1 mode. This software reset has the same effect as the RESET pin. See the Reset
Operation section for the default settings.
#
Table 194 - Global Control0 Register (R/W Address 900) (E1)
not used.
The Transmit Byte Count Register indicating the length of the data portion of the packet
about to be transmitted. This is the size of the data and not the address, flags or FCS.
The Transmit Byte Counter position Y1C determines the number of bytes that have
been sent from the Transmit FIFO.
not used.
This eight bit word is tagged with the two status bits from control register 1 (EOP and
FA), and the resulting 10 bit word is written to the TX FIFO. The FIFO status is not
changed immediately after a write or read occurs. It is updated after the data has
settled and the transfer to the last available position has finished. Note that when the
HDLC is connected to a T1 channel, the least significant bit in the FIFO is sent first.
16.384 MHz
Clock
4.096 MHz
Table 193 - TX Byte Count Register(YF6) (E1)
Table 192 - TX Fifo Write Register(YF5) (E1)
11
and A
8
being high and A
Zarlink Semiconductor Inc.
Frame Pulse
2.048 Mb/s
8.192 Mb/s
MT9072
Functional Description
216
Functional Description
Functional Description
10
and A
System Bus
2.048 Mb/s
8.192 Mb/s
9
being low)
Data Sheet