mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 25

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
LQFP
106
126
146
107
127
147
108
132
148
26
46
66
86
27
47
67
87
28
48
68
88
6
7
8
Pin #
LBGA
P12
P14
K16
E14
P15
E15
R10
P16
E16
J13
J14
D4
N4
R9
P6
E1
P1
P7
E2
P2
P8
J2
J3
J4
TPOS[0]
TPOS[1]
TPOS[2]
TPOS[3]
TPOS[4]
TPOS[5]
TPOS[6]
TPOS[7]
TNEG[0]
TNEG[1]
TNEG[2]
TNEG[3]
TNEG[4]
TNEG[5]
TNEG[6]
TNEG[7]
TXCL[0]
TXCL[1]
TXCL[2]
TXCL[3]
TXCL[4]
TXCL[5]
TXCL[6]
TXCL[7]
Name
Type
IO
O
O
Transmit Positive. This pin is an output for the transmit side of the
framer; it typically interfaces to an LIU. If used by itself it can provide
single rail NRZ (Non Return to Zero) data. If TPOS is used in
conjunction with TNEG it can provide dual rail NRZ data or dual rail RZ
(Return to Zero) data. The clock at the TXCL pin is used to clock data
out of the TPOS pin. Pins TPOS[0-7] are used for Framers[0-7]
respectively.
In T1 mode, line codes are selected with control bits: TZCS2-0, TPDV,
TXB8ZS, RZNRZ and UNIBI (Address Y01). T1 mode is selected if the
T1E0 bit (Address 900) is 1.
In E1 mode, line codes are selected with control bits: COD0-1 and
THDB3 (Address Y02). E1 mode is selected if the T1E0 bit (Address
900) is 0.
Transmit Negative. This pin is an output for the transmit side of the
framer; it typically interfaces to an LIU. TNEG is used in conjunction
with TPOS to provide dual rail NRZ (Non Return to Zero) data or dual
rail RZ (Return to Zero) data. The clock at the TXCL pin is used to
clock data out of the TNEG pin. Pins TNEG[0-7] are used for
Framers[0-7] respectively.
In T1 mode, line codes are selected with control bits: TZCS2-0, TPDV,
TXB8ZS, RZNRZ and UNIBI (Address Y01). T1 mode is selected if the
T1E0 bit (Address 900) is 1.
In E1 mode, line codes are selected with control bits: COD0-1 and
THDB3 (Address Y02). E1 mode is selected if the T1E0 bit (Address
900) is 0.
1.544/2.048 MHz Transmit Clock. This pin accepts/outputs a clock
that is used to clock data out of the transmit side of the framer on pins
TPOS and TNEG. If TPOS/TNEG are configured for RZ output then
the rising edge of the clock is used to clock TPOS/TNEG data. If
TPOS/TNEG are configured for NRZ output then either a rising or
falling TxCL edge can be selected to clock TPOS/TNEG data. Pins
TxCL[0-7] are used for Framers[0-7] respectively.
In T1 mode this pin is an input. The 1.544 MHz transmit clock is
typically provided by an external PLL (Phase Lock Loop) or LIU. An
active rising or falling edge is selected with the CLKE bit (Address
Y01). See Figure 52.
In E1 mode this pin is an output. The 2.048 MHz transmit clock is
synchronous with the 4.096 MHz ST-BUS clock input to pin CKi. An
active rising or falling edge is selected with the T2OP bit (Address
Y02). See Figure 71.
Zarlink Semiconductor Inc.
MT9072
25
Description (see Notes 1 to 7)
Data Sheet