mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 39

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

2.6
The T1 ESF Facility Data Link (FDL) bits can be accessed in the following three ways: Through the data link pins
TxDL, RxDL, RxDLC and TxDLC or through internal registers for Bit Oriented Messages or through the embedded
HDLC.
In E1 mode the Sa bits (bits 4-8 of the non-frame alignment signal) can be accessed in four ways: Through data
link pins TxDL, RxDL, RxDLC and TxDLC or through single byte transmit and receive registers or through five
byte transmit and receive national bit buffers or through the embedded HDLC.
2.7
Robbed bit signaling and channel associated signaling information can be accessed two ways: Via the microport;
via the CSTi and CSTo pins. Signaling information is frozen upon loss of multiframe alignment.
In T1 mode the MT9072 supports AB and ABCD robbed bit signaling. Robbed bit signaling can be enabled on a
channel by channel basis.
In E1 mode the MT9072 supports Channel Associated Signaling (CAS) multiframing.
2.8
MT9072 supports Common Channel Signaling (CCS) with the embedded HDLCs and with the capability to map
external HDLCs to/from the transmit/receive timeslots.
In T1 mode CCS is supported in any one channel by using the embedded HDLC. Alternatively, the CSTi and CSTo
pins can be used to map an external HDLC channel to/from any one transmit/receive T1 channel.
In E1 mode CCS is supported in any one timeslot by using the embedded HDLC. Alternatively, the CSTi and CSTo
pins can be used to map three external HDLC channels to/from any of transmit/receive E1 timeslots 15, 16 and 31.
2.9
The MT9072 provides one embedded HDLC per framer with 32 byte deep transmit and receive FIFOs.
In T1 mode the embedded HDLC can be assigned to the FDL or any channel. It can operate at 4 kbit/s (Data Link),
56 kbit/s or 64 kbit/s.
In E1 mode the embedded HDLC can be assigned to timeslot zero Sa bits (bits 4-8 of the non-frame alignment
signal), or any other timeslot. It can operate at 4, 8, 12, 16, 20 (Data Link) or 64 kbit/s.
2.10
The MT9072 has a comprehensive suite of performance monitoring and debugging features. These include error
counters, loopbacks, deliberate error insertion and a 2
2.11
The MT9072 provides a comprehensive set of maskable interrupts. Interrupt sources consist of synchronization
status, alarm status, counter indication and overflow, timer status, slip indication, maintenance functions and
receive signaling bit changes.
Access to the Maintenance Channel
Robbed Bit Signaling/Channel Associated Signaling
Common Channel Signaling
HDLCs
Interrupts
Performance Monitoring and Debugging
Zarlink Semiconductor Inc.
MT9072
15
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–1 QRS/PRBS generator/detector.
Data Sheet