mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 49

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

5.2.1
Timeslot 0 of every 125 us frame is reserved for basic frame alignment and contains a Frame Alignment Signal
(FAS) or a Non-Frame Alignment Signal (NFAS). FAS and NFAS occur in consecutive basic frames as shown in
Table 12.
Bit one of the FAS can be either a CRC-4 remainder bit or an international usage bit.
Bit one of the NFAS can be either a CRC-4 multiframe alignment signal, an E-bit or an international usage bit. Refer
to national standards bodies for specific requirements.
Bit two of the FAS and NFAS is used to distinguish between FAS (bit two = 0) and NFAS (bit two = 1) frames.
Bits two to eight of the FAS are used for basic frame alignment. Basic frame alignment is initiated by a search for
the bit sequence 0011011 which appears in the last seven bit positions of the FAS, see the Frame Algorithm
section.
Bit three of the NFAS (designated as “A”), the Remote Alarm Indication (RAI), is used to indicate the near end basic
frame synchronization status to the far end of a link. Under normal operation, the A (RAI) bit should be set to 0,
while in alarm condition, it is set to 1.
Bits four to eight of the NFAS (i.e., Sa4-8) are additional spare bits which may be used as follows:
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•
•
•
Register
Address
Sa4-8 may be used in specific point-to-point applications (e.g., transcoder equipments conforming to G.761)
Sa4 may be used as a message-based data link for operations, maintenance and performance monitoring
Sa5-Sa8 are for national usage but are also available from the Data link interface(TxDL,RxDL)
Note that for simplicity all Sa bits including Sa4 are collectively called national bits throughout this document.
See the Data Link section for accessing the national bits.
Y27
Y2A
Y34
Y35
Y44
Y45
E1 Basic Framing (Timeslot 0)
Performance Presistent Latched
Status Register
CRC-4 Error Counter Latch.
Sync, CRC-4
Remote,Alarm,MAS and Phase
Status Register
Counter Indication and Counter
Overflow Interrupt status
Sync Interrupt Mask Register
Counter Indication and Counter
Overflow Interrupt Mask
Register
Register
Table 11 - Registers Related to Framing for MT9072 (E1)
Zarlink Semiconductor Inc.
This register latches the detection of loss(LOSSP) and basic
frame sync(BSYNCP).
This a a sampled version of Y19 latched every one sec.
These are the interrupt status bits for BSYNC, Receive Multiframe
Alignment Interrupt etc.
This register represents the interrupt status bits for counter
overflows, counter indications etc.
This is the mask register for the events in register Y34.
This is the mask register for the events in register Y35.
MT9072
49
Description
Data Sheet