mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 61

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mt9072av2

Manufacturer Part Number
mt9072av2
Description
Octal T1/e1/j1 Framer
Manufacturer
Zarlink Semiconductor
Datasheet

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For the National Bit Buffer transmit registers DL access to be enabled the SA4SS to SA8SS(register Y08) are set to
00.
Similarly, the DL data received on the PCM30 link is output to the National Bit Buffer receive data registers (register
address YC0-YC4), corresponding to bit positions as shown in Table 18. However, the National Bit Buffer receive
data registers are always enabled, regardless of the above control bit settings(SA4SS to SA8SS). Received DL
Data should be read from the National Bit Buffer receive data registers immediately following the CALN status
indication (during basic frame 0) and before the start of basic frame 1.
In order to facilitate conformance to ETS 300 233, three maskable interrupts are available for change of state of Sa
bits in the receive National Bit Buffer. These include Eight Consecutive Sa6 Nibbles (Sa6N8), Sa6 Nibble Change
(Sa6N) and Sa Nibble Change (SaN). See the detailed descriptions for these status bits provided in the CAS,
National, CRC-4 Local and Timer Interrupt Status Register (address Y36).
7.2.3
When the ST-BUS Data Link (DL) access is enabled, the setting of the 8 ST-BUS DSTi data bits determine the Data
Link (DL) output on the PCM30 link corresponding to bit positions one to three and Sa4-8 over each Non-Frame
Alignment Signal (NFAS) frame. Data for DL transmission should be written to DSTi immediately following the
NFAS frame (during FAS frames) and before the start of the next NFAS frame.
The ST-BUS Data Link (DL) access is enabled if the Sa Source Select Bits (Sa4SS-SA8SS) are set to ’10’ in
register Y08. ST-BUS DSTi timeslot 0 bits will be transmitted as NFAS bits on the PCM30 link, as shown in Table 19
(bit positions one to eight of timeslot zero, of odd CRC-4 frames 1, 3, 5, 7, 9, 11, 13, 15).
The DL data received on the PCM30 link is always output to ST-BUS DSTo timeslot 0 during NFAS frames,
regardless of the settings of SA4SS to SA8SS.
Transmit
TN0
TN1
TN2
TN3
TN4
E1 Data Link (DL) ST-BUS Access
Address
Addressable Bytes
YB0
YB1
YB2
YB3
YB4
Table 18 - MT9072 National Bit Buffers (E1)
Receive
RN0
RN1
RN2
RN3
RN4
Zarlink Semiconductor Inc.
Address
YC0
YC1
YC2
YC3
YC4
MT9072
61
B7
S
S
S
S
S
F1
a4
a5
a6
a7
a8
NFAS Frames of a CRC-4 Multiframe
B6
S
S
S
S
S
F3
a4
a5
a6
a7
a8
B5
S
S
S
S
S
F5
a4
a5
a6
a7
a8
B4
F7
S
S
S
S
S
a4
a5
a6
a7
a8
F9
B3
S
S
S
S
S
a4
a5
a6
a7
a8
F11
B2
S
S
S
S
S
a4
a5
a6
a7
a8
Data Sheet
F13
B1
S
S
S
S
S
a4
a5
a6
a7
a8
F15
B0
S
S
S
S
S
a4
a5
a6
a7
a8

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