mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 77

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

processing a frame, thus if the receiver is enabled in the middle of an incoming packet it will ignore that packet and
wait for the next complete one.
The receive CRC can be monitored in the Rx CRC Register(Y1E). This register contains the actual CRC sent by the
other transmitter in its original form; that is, MSB first and bits inverted. These registers are updated at each end of
packet (closing flag) received and therefore should be read when an end of packet is received so that the next
packet does not overwrite the registers.
10.0
10.1
The control and status of the MT9072 is achieved through a non-multiplexed parallel microprocessor port capable
of accommodating 12 address bits and 16 data bits. The parallel port may be configured for Motorola style control
signals (by setting pin I/M low) or Intel style control signals (by setting pin I/M high).
10.1.1
The controlling microprocessor gains access to specific registers and framers in the MT9072 through a single step
process. Each of the eight internal framers is identified by the upper four address bits (A11-A8). Addresses 0XX,
1XX, 2XX... 7XX (where X indicates any hex number between 0 and F) access framers 0,1,2... 7 respectively.
Address 8XX accesses all 8 framers simultaneously for processor writes. In addition, there are seven registers
which are global to all eight framers; the Interrupt Vector and the Interrupt Vector Mask Registers, ST-BUS Select
Register and ST-BUS analyzer control registers. These are accessed with addresses 900 to 911. Throughout this
document, the upper four address bits (A11-A8) are referred to as Y, (where Y indicates any hex number between 0
and 7).
Each register in the eight internal framers is identified by the lower eight address bits (A7-A0). All registers provided
in each of the eight framers are identical, with identical lower eight bit addresses. The lower eight address bits are
partitioned such that the upper four bits (A7-A4) identify the register group (i.e., Control, Status, Interrupt Mask etc.)
and the lower four bits (A3-A0 identify the particular register in the register group (i.e., Tx Alarm Control
Word,signaling Control Word etc.), see Table 34.
See Figures 22 and 23 for processor timing requirements. See the Registers section for detailed register
descriptions.
The MT9072 includes a status register which contains a15 bit identification code (address 912) for the MT9072.
This code identifies the marketing revision. This byte allows user software to track device revisions, and device
variances and provide system variations if necessary. Refer to the registers section for details.
Selects the framer(s) (i.e., 0, 1, 2, 3,
4, 5, 6, 7,all, global)
Processor Interface (A11-A0, D15-D0, I/M, DS, R/W, CS, IRQ, Pins)
MT9072 Access and Control
Framer and Register Access
A
11
,A
10
,A
9
,A
8
Table 34 - Framer and Register Access
Selects the register group (i.e.,
Control, Status, Interrupt Mask etc.)
Zarlink Semiconductor Inc.
MT9072
A
Address
7
,A
77
6
,A
5
A
4
Selects the particular register in the
register group (i.e., PRBS Error
Counter etc.)
A
3
,A
2
,A
1
,A
0
Data Sheet