mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 91

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

14.1.5
If the control bit ADSEQ is one (register address Y01), the Mu-law digital milliwatt sequence (Table 45) defined by
G.711, is available to be transmit on any combination of selected channels. The channels are selected by setting
the TTSTn control bit (register address Y90-YA7). The same sequence is available to replace received data on any
combination of DSTo channels. This is accomplished by setting the RRSTn control bit (register address Y90-YA7)
for the corresponding channel. Note that Bit 1 is the sign bit and is sent first.
14.1.6
The alarms shown in Table 46 are detected by the receiver. The status register bits provide real time status of the
alarm, while the interrupt status registers bits provide latched status indications which are cleared when read. Each
interrupt status register may also generate a maskable interrupt. The possible transmitted alarms are also shown in
the table. See the register bit descriptions for details.
D4 Yellow Alarm. This bit is set if bit position 2 of virtually every
DS0 channel is a zero for a period of 600 milliseconds. The alarm is
tolerant of errors by permitting up to 16 ones in a 48 millisecond
integration period. The alarm clears in 200 milliseconds after being
removed from the line.
D4 Yellow Alarm - 48 millisecond sample. This bit is set if bit
position 2 of virtually every DS0 channel is a zero for a period of 48
milliseconds. The alarm is tolerant of errors by permitting up to 16
ones in the integration period. This bit is updated every 48
milliseconds.
Hex
1E
0B
0B
1E
1E
8B
8B
9E
T1 Mu-law Milliwatt
T1 Alarms
Bit 1
0
0
0
0
1
1
1
1
Description
Bit 2
0
0
0
0
0
0
0
0
Table 45 - Mu Law Digital Milliwatt Pattern (T1)
Table 46 - Alarm Control and Status Bits (T1)
Control/Status Register
Bit 3
0
0
0
0
0
0
0
0
PCM 24 Payload Data
Zarlink Semiconductor Inc.
MT9072
Bit 4
91
1
0
0
1
1
0
0
1
Bit 5
1
1
1
1
1
1
1
1
D4YALM
D4Y48
Bit
Bit 6
1
0
0
1
1
0
0
1
Address
Y10
Y10
Bit 7
D4YALMI
D4Y48I
1
1
1
1
1
1
1
1
Interrupt Status
Bit
Register
Data Sheet
Address
Bit 8
Y35
Y35
0
1
1
0
0
1
1
0