mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 135
mt90502ag2
Manufacturer Part Number
mt90502ag2
Description
Multi-channel Aal2 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90502AG2.pdf
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Address: 402h
Label: status0
Reset Value: 0000h
cpu_buffer_overflow
aal0_overflow
error_overflow
reserved
Address: 404h
Label: status0_ie
Reset Value: 0000h
cpu_buffer_overflow_ie
aal0_overflow_ie
error_overflow_ie
reserved
Address: 410h
Label: silent_pattern_reg
Reset Value: 00FFh
write_back_pattern
reserved
Label
Label
Label
Bit Position
Bit Position
Bit Position
15:3
0
1
2
15:8
15:3
7:0
0
1
2
Table 75 - RX Interrupt Enable Register
Table 76 - PCM Silent Pattern Register
Table 74 - RX Status Register
Type
ROL
ROL
ROL
ROL
Type
RW
RW
Type
RO
Zarlink Semiconductor Inc.
IE
IE
IE
CPU Destined CPS-Packet Buffer Overflow.
Overflow in the receive AAL0 cell buffer.
Overflow in the error/event structure buffer.
Reserved. Always read as “0000_0000_0000_0”
MT90502
PCM Silent pattern written back to RX circular buffers by RX
TDM module (only if enabled in PCM RX Control Memory
structure)
Reserved. Must always be “0000_0000”
When ‘1’ and the corresponding status bit is ‘1’ an interrupt
will be generated.
When ‘1’ and the corresponding status bit is ‘1’ an interrupt
will be generated.
When ‘1’ and the corresponding status bit is ‘1’ an interrupt
will be generated.
Reserved. Always read as “0000_0000_0000_0”
135
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Description
Description
Data Sheet
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