zl50017 Zarlink Semiconductor, zl50017 Datasheet - Page 22

• Manufacturer Part Number: zl50017
• Description: 1 K Digital Switch
• Manufacturer: Zarlink Semiconductor

6.0
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform timeslot interchange functions with different throughput delay
capabilities on a per-channel basis. For voice applications, select variable throughput delay to ensure minimum
delay between input and output data. In wideband data applications, select constant delay to maintain the frame
integrity of the information through the switch. The delay through the device varies according to the type of
throughput delay selected by the V/C (bit 14) in the Connection Memory Low when CMM = 0.
6.1
Variable delay mode causes the output channel to be transmitted as soon as possible. This is a useful mode for
voice applications where the minimum throughput delay is more important than frame integrity. The delay through
the switch can vary from 7 channels to 1 frame + 7 channels. To set the device into variable delay mode, VAREN
(bit 4) in the Control Register (CR) must be set before V/C (bit 14) in the Connection Memory Low when CMM = 0.
If the VAREN bit is not set and the device is programmed for variable delay mode, the information read on the
output stream will not be valid.
In variable delay mode, the delay depends on the combination of the source and destination channels of the input
and output streams.
For example, if Stream 4 Channel 2 is switched to Stream 5 Channel 9 with variable delay, the data will be output in
the same 125 µs frame. Contrarily, if Stream 6 Channel 1 is switched to Stream 9 Channel 3, the information will
appear in the following frame.
T = Delay between input and output
STio5
STio9
STi4
CH2
CH9
STi6
CH1
CH3
n = output channel number
m = input channel number
Variable Delay Mode
Data Delay Through the Switching Paths
L = last channel = 31, 63, 127 or 255 for 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps respectively.
L-2
L-2
L-2
L-2
L-1 CH0 CH1 CH2 CH3
L-1 CH0 CH1 CH2 CH3
L-1 CH0 CH1 CH2 CH3
L-1 CH0 CH1 CH2 CH3
Figure 12 - Data Throughput Delay for Variable Delay
Table 1 - Delay for Variable Delay Mode
1 frame - (m-n)
CH4 CH5 CH6
CH4 CH5 CH6
CH4 CH5 CH6
CH4 CH5 CH6
n-m <= 0
Zarlink Semiconductor Inc.
ZL50017
Frame N
22
CH7 CH8 CH9
CH7 CH8 CH9
CH7 CH8 CH9
CH7 CH8 CH9
0 < n-m < 7
1 frame + (n-m)
STio < STi
L-2
L-2
L-2
L-2
n-m = 7
L-1 CH0 CH1 CH2 CH3
L-1 CH0 CH1 CH2 CH3
L-1 CH0 CH1 CH2 CH3
L-1 CH0 CH1 CH2 CH3
STio >= STi
Frame N + 1
n-m
Data Sheet
n-m > 7