ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 171

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
3.15: DMAQS System Descriptor Address
The upper 57 bits contain the address of the current descriptor block and the lower seven bits contain the
number of descriptors in the chain that remain to be processed. When doing register-based DMAs, the low
six bits are set to "000001" when the DMAQS Transfer Count and Flag Register is written. If DMA descriptors
are used for DMA transfers, this register will contain the system address of the current descriptor block and
the number of descriptors that remain to be processed. This address may be queued on DMA completion to
correlate DMA transfers with system control blocks. In 32-bit addressing mode, the low-order 32 bits of the
register are written, and the high-order 32 bits are reset when the register is loaded.
Length
Type
Address
Power on Value
Restrictions
3.16: DMAQS Checksum Register
This register contains the accumulated checksum. This register contains the accumulated checksum value. It
can also be used to initialize the checksum with a seed value. The most significant bit contains the alignment
state (1 = odd, 0 = even alignment). The alignment state is significant between subsequent checksummed
DMAs.
This register can be read at four different addresses. The base address returns the unmodified accumulated
checksum. The base address +4 returns the inverted accumulated checksum. The base address + 8 returns
the byte-swapped accumulated checksum. The base address + 12 returns the inverted byte-swapped accu-
mulated checksum.
Length
Type
Address
pnr25.chapt04.01
August 14, 2000
64 bits
Read/Write
Queue 0
Queue 1
Queue 2
X’0000000000000000’
This register should not be written if descriptors are going to be used to set up DMA
transfers. If it is used, it must be written to 0 before descriptors are enqueued.
17 bits
Read/Write
Q0 Sum
Q0 Inv Sum
Q0 Swapped Sum
Q0 Inv Swapped
Q1 Sum
Q1 Inv Sum
Q1 Swapped Sum
Q1 Inv Swapped
Q2 Sum
Q2 Inv Sum
XXXX 0648
XXXX 06C8
XXXX 0748
XXXX 0654
XXXX 065C
XXXX 0664
XXXX 066C
XXXX 06D4
XXXX 06DC
XXXX 06E4
XXXX 06EC
XXXX 0754
XXXX 075C
IBM Processor for Network Resources
DMA QUEUES (DMAQS)
Page 171 of 676
IBM3206K0424