ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 236

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ibm3206k0424

Manufacturer Part Number
ibm3206k0424
Description
Ibm Processor For Network Resources
Manufacturer
ETC-unknow
Datasheet
IBM3206K0424
IBM Processor for Network Resources
ATM Packet/Control Memory Arbitration Logic (ARBIT)
Page 236 of 676
31-24
23-16
Bit(s)
15-8
7-0
The value loaded into these bits defines what memory event is counted by performance counter 3. These bits are defined as
follows:
Bit 7: When reset, Control Memory events are counted, when set, Packet Memory events are counted by the associated
counter.
Bit 6: Reset the associated counter to 0. This bit will be reset by the hardware, during the same cycle that the counter is being
reset.
Bit 5: Reserved
Bits 4-0: Cycle type, encoded as:
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
The value loaded into these bits define what memory event is counted by performance counter 2.
The value loaded into these bits define what memory event is counted by performance counter 1.
The value loaded into these bits define what memory event is counted by performance counter 0.
Any Request
Any Request between 0 and 4 bytes
Any Request between 5 and 8 bytes
Any Request between 9 and 16 bytes
Any Request between 17 and 32 bytes
Any Request between 33 and 64 bytes
Any Request between 65 and 128 bytes
Reserved
Any Read Request
Any Read Request between 0 and 4 bytes
Any Read Request between 5 and 8 bytes
Any Read Request between 9 and 16 bytes
Any Read Request between 17 and 32 bytes
Any Read Request between 33 and 64 bytes
Any Read Request between 65 and 128 bytes
Reserved
Any Write Request
Any Write Request between 0 and 4 bytes
Any Write Request between 5 and 8 bytes
Any Write Request between 9 and 16 bytes
Any Write Request between 17 and 32 bytes
Any Write Request between 33 and 64 bytes
Any Write Request between 65 and 128 bytes
Reserved
Read op latency
Write op latency
Reserved
Reserved
Reserved
Reserved
Hold Current Count
Every Cycle
Description
pnr25.chapt04.01
August 14, 2000
Preliminary

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