ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 242

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
8.3: BCACH Interrupt Enable Register
The low eight bits in this register allow the user to selectively determine which bits in the BCACH status regis-
ter will cause processor interrupts. A ‘0’ in a bit position masks interrupts from the corresponding bit location
in the BCACH status register. A ‘1’ in a bit position allows interrupts for the corresponding bit in the BCACH
status register. The high eight bits in this register allow the user to selectively determine which bits in the
BCACH status register will lock the cache. A ‘1’ in any bit position forces the cache to lock if the correspond-
ing bit is set in the BCACH status register. If the cache locks, all status regarding the cache lines is main-
tained until the cache enable bits in the control register are turned off.
See Note on Set/Clear Type Registers on page 93 for more details on addressing.
Length
Type
Address
Power On Value
Restrictions
8.4: BCACH High Priority Timer Value
This register defines the number of 15 ns cycles that will pass from the time that a valid PCI bus request is
raised to BCACH until BCACH will raise its high priority request to the memory controllers. A value of ‘0’ in
this register disables this function completely.
Length
Type
Address
Power On Value
Restrictions
The Bus DRAM Cache Controller (BCACH)
Page 242 of 676
7
Bit(s)
7-0
Number of 15 ns Cycles
6
5
Specifies the number of 15 ns cycles before a high priority request.
For example, if bit 3 is set to ‘1’ and all others are set to ‘0’, then 6 cycles (120 ns) will pass between receipt of request and
sending request to controllers.
4
3
2
1
0
16 bits
Clear/Set
XXXX 1010 and 014
X’FFFF’
None
8 bits
Read/Write
XXXX 1040
X’40’
None
Description
pnr25.chapt04.01
August 14, 2000
Preliminary