ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 404

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
Moving Cells To and From the IBM3206K0424
14.1: LINKC Global Control Register
This register contains the information which controls the operation of LINKC. These controls affect all config-
urations. See Note on Set/Clear Type Registers on page 93 for more details on addressing.
Length
Type
Address
Power On Value
Restrictions
The PHY Interface (LINKC)
Page 404 of 676
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit(s)
31
30
29
28
27
Utopia Cell
Utopia Cell
Utopia Cell
Utopia Cell
Utopia Cell
Interface
Enable LINKC
Reserved
Allow RX side to stall
Ignore RX Empty signal
Ignore TX Full signal
Name
32 bits
Clear/Set
XXXX 0B30 AND 34
X’C0000344’
None
Data Payload
48
48
48
48
48
This bit, when set to ’1’ will enable LINKC. The default for this bit is ’1’.
Reserved.
When this bit is set, the RX side is allowed to stall. This means that the IBM3206K0424
is allowed to park on a port until the port has data for the IBM3206K0424. This bit
should be set if you are talking to a single drop POS-PHY device that doesn't have
address pins and the IBM3206K0424 is being run in multi-drop mode.
When this bit is set the EMPty signal will be ignored and it is always assumed the PHY
has data. The default for this bit is ’0’.
When this bit is set the Full signal will be ignored and it is always assumed the PHY
has room. The default for this bit is ’0’.
Cell
52
53
54
55
56
Cycles for Eight-bit bus
Description
52
53
54
55
56
9
8
7
6
5
Cycles for 16-bit bus
4
pnr25.chapt05.01
August 14, 2000
3
26
27
27
28
28
Preliminary
2
1
0