ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 512

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
20.2: Software Reset Enable Register
This register protects the Software Reset Register. If this register is not set, then a reset will not occur. Write
a X’B4’ to this register to enable software reset. A software reset will clear this register.
Length
Type
Address
POR Value
Restrictions
20.3: Software Reset Register
This register generates a scan path flush reset of the chip, or software initiated run of BIST, with the excep-
tion of the registers in the reset entity.
Length
Type
Address
POR Value
Restrictions
Reset and Power-on Logic (CRSET)
Page 512 of 676
3
Bit(s)
2
3
2
1
0
1
PCORE Processor Reset
Total Software Reset
Run BIST
Software Reset
0
Name
8 bits
Read/Write
XXXX 0504
X’0’
None
4 bit
Write Only
XXXX 0508
B’0’
Writing to this register without first setting the Software Reset Enable Register will
have no affect. The register will not be set, thus the order of writing the enable and
the software reset is important; the enable must be written first. Additionally, all
current operations being performed by the IBM3206K0424 must be terminated
before doing a reset operation. A minimum number of enable bits to turn off would
be bits four, five, and six in INTST Control Register and bit 2 in PCINT Config Word
1.
Writing this bit to a ’1’ causes the internal processor core to reset.
Writing this bit to a ’1’ causes software reset and will be cleared after the software
reset has occurred. The config registers in PCINT will also be put to their reset state.
Writing this bit to a ’1’ causes BIST to run and will be cleared after the software reset
has occurred. This function is primarily for pre-loading the BIST registers to get more
test coverage.
Writing this bit to a ’1’ causes software reset and will be cleared after the software
reset has occurred. The config registers in PCINT will not be affected by this reset.
Description
pnr25.chapt05.01
August 14, 2000
Preliminary