ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 7

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
nrm.toc.01
August 14, 2000
The Bus DRAM Cache Controller (BCACH) ..................................................................................... 238
Buffer Pool Management (POOLS) ................................................................................................... 247
ARBIT Control Lock Entity Enable Register .................................................................................. 224
ARBIT Control Config Register ...................................................................................................... 225
ARBIT Packet Priority Resolution Register High ........................................................................... 225
ARBIT Packet Priority Resolution Register Low ............................................................................ 227
ARBIT Packet Entity Error Mask Register ..................................................................................... 228
ARBIT Packet Error Source Register ............................................................................................ 229
ARBIT Packet Winner Register ..................................................................................................... 230
ARBIT Packet Address Register A ................................................................................................ 231
ARBIT Packet Address Register B ................................................................................................ 231
ARBIT Packet Length Register ...................................................................................................... 232
ARBIT Packet Lock Entity Enable Register ................................................................................... 233
ARBIT Packet Config Register ...................................................................................................... 234
ARBIT Performance Counter Control ............................................................................................ 235
Arbit Memory Performance Counter .............................................................................................. 237
BCACH Control Register ............................................................................................................... 239
BCACH Status Register ................................................................................................................ 241
BCACH Interrupt Enable Register ................................................................................................. 242
BCACH High Priority Timer Value ................................................................................................. 242
BCACH Line Tag Registers ........................................................................................................... 243
BCACH Line Valid Bytes Register ................................................................................................. 244
BCACH Line Status Register ......................................................................................................... 245
BCACH Cache Line Array ............................................................................................................. 246
Basic Operation in Real Memory Mode ......................................................................................... 247
Basic Operation in Virtual Memory Mode ...................................................................................... 247
Resource Controls ......................................................................................................................... 247
Virtual Memory Overview .............................................................................................................. 248
POOLS Get Pointer Primitive ........................................................................................................ 252
POOLS Free Pointer Primitive ....................................................................................................... 253
POOLS Common Pools Count Registers ...................................................................................... 253
POOLS Client Thresholds Array .................................................................................................... 254
POOLS User Threshold and Client Active Packet Count Array .................................................... 255
POOLS Pointer Queues DRAM Head Pointer Offset Address Register ....................................... 256
POOLS Pointer Queues DRAM Tail Pointer Offset Address Register .......................................... 257
POOLS Pointer Queues DRAM Lower Bound Address Register .................................................. 258
POOLS Pointer Queues DRAM Upper Bound Register ................................................................ 259
POOLS Pointer Queues Length Registers .................................................................................... 261
POOLS Interrupt Enable Register ................................................................................................. 261
POOLS Event Enables .................................................................................................................. 262
POOLS Event Hysteresis Register ................................................................................................ 262
POOLS Event Data Register ......................................................................................................... 263
POOLS Status Register ................................................................................................................. 265
POOLS Control Register ............................................................................................................... 267
POOLS Buffer Threshold Registers 0-4 ........................................................................................ 269
POOLS Index Threshold Registers 0-4 ......................................................................................... 269
POOLS Last Primitive Trap Register ............................................................................................. 270
POOLS Last Buffer Map Read on Free Register .......................................................................... 270
POOLS Error Lock Enable Register .............................................................................................. 270
POOLS Packet and Control Memory Access Threshold ............................................................... 271
POOLS Buffer Map Group ............................................................................................................. 271
IBM Processor for Network Resources
IBM3206K0424
Page 7