am79c984a Advanced Micro Devices, am79c984a Datasheet
am79c984a
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am79c984a Summary of contents
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... PRELIMINARY Am79C984A enhanced Integrated Multiport Repeater (eIMR™) DISTINCTIVE CHARACTERISTICS Repeater functions comply with IEEE 802.3 Repeater Unit specifications Four integral 10BASE-T transceivers with on- chip filtering that eliminate the need for external filter modules on the 10BASE-T transmit-data (TXD) and receive-data (RXD) lines One Reversible Attachment Unit Interface (RAUI™ ...
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... SPEED OPTION Not Applicable DEVICE NUMBER/DESCRIPTION Am79C984A enhanced Integrated Multiport Repeater (eIMR) Valid Combinations list configurations planned to be supported in volume for this device. Consult JC, KC\W the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C984A Valid Combinations ...
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... BLOCK DIAGRAM Am79C984A 3 ...
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... PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus) Am79C974 PCnet™-SCSI Combination Ethernet and SCSI Controller for PCI Systems Am79C983 Integrated Multiport Repeater 2 (IMR2™) Am79C985 enhanced Integrated Multiport Repeater Plus (eIMR+™ Am79C984A ...
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... Chip Programmable Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 Alternate AUI Partitioning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 Alternate TP Partitioning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 AUI Port Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 AUI Port Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 TP Port Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 TP Port Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 Disable Link Test Function (Per TP port 1-52 Enable Link Test Function (Per TP port 1-52 Disable Link Pulse (Per TP Port 1- Am79C984A 5 ...
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... Internal Arbitration Mode Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57 IMR+ Mode External Arbitration 1-57 Visual Status Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-59 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-60 OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-60 DC CHARACTERISTICS over operating ranges unless otherwise specifi 1-60 SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-62 KEY TO SWITCHING WAVEFORMS 1-64 SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-64 SWITCHING TEST CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- Am79C984A ...
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... SELI_1 eIMR Am79C984A Am79C984A LDC2 73 LDC1 72 LDC0 71 VDD 70 LDGB 69 LDGA 68 LDB4 67 DVSS 66 LDA4 65 LDB3 64 LDA3 63 DVSS 62 LDB2 61 LDA2 60 VDD ...
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... Am79C984A Am79C984A VDD LDC2 LDC1 LDC0 VDD LDGB LDGA LDB4 DVSS LDA4 LDB3 LDA3 DVSS LDB2 LDA2 VDD LDB1 LDA1 NC DVSS LDB0 LDA0 ACT7 ACT6 ...
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... SELI[1:0] DO+ DO– DI+ SI DI– Am79C984 CI+ SO CI– SCLK AMODE LDA[4:0], LDB[4:0] LDGA, LDGB LDC[2:0] ACT[7:0] CLK RST AUI Repeater State Machine Am79C984A Twisted Pair Ports (4 Ports) AUI LED Interface 20650A-4 20650B-4 Expansion Port Twisted Pair Port 3 20650A-5 20650B-5 9 ...
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... SELO 54 34 COL 55 35 DVSS 56 36 ACK 57 37 DAT 58 38 VDD 59 39 JAM DVSS Am79C984A Pin Name Pin No. Pin Name SO 64 LDA3 SCLK 65 LDB3 VDD 66 LDA4 ACT0 67 DVSS ACT1 68 LDB4 ACT2 69 LDGA DVSS 70 LDGB ACT3 71 VDD ACT4 ...
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... SCLK 67 43 VDD 68 44 ACT0 69 45 ACT1 70 46 ACT2 71 47 DVSS 72 48 ACT3 73 49 ACT4 74 50 ACT5 75 Am79C984A Pin Name Pin No. Pin Name ACT6 76 LDC2 ACT7 80 VDD LDA0 81 TXD0+ LDB0 82 TXD0- DVSS 83 AVSS NC 84 TXD1+ ...
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... Input/Output, Active LOW, Open Drain When asserted, COL indicates that more than one eIMR device is active. Each eIMR device generates the Col- lision Jam sequence independently. When the eIMR de- vice is configured for Internal Arbitration mode, COL is Am79C984A or SELI is driven by SELO from 0 1 ...
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... This pin is a 20-MHz clock input. REXT External Reference Input This pin is used for an internal current reference. It must be tied to VDD via a 13-k resistor with 1% tolerance. VDD 0-4 Power . 0-2 Power Pin This pin supplies power to the device. Am79C984A , LDGA, and LDGB LED is pro- , SI, and AMODE pins, 0-1 13 ...
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... AVSS Analog Ground Ground Pin This pin is the ground reference for the differential receivers and drivers DVSS Digital Ground Ground Pin This pin is the ground reference for all the digital logic in the eIMR device. Am79C984A ...
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... FUNCTIONAL DESCRIPTION The Am79C984A eIMR device is a single-chip imple- mentation of an IEEE 802.3/Ethernet repeater (or hub offered with four integral 10BASE-T ports plus one RAUI port comprising the basic repeater. The eIMR de- vice is also expandable, enabling the implementation of high port count repeaters based on several eIMR de- vices ...
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... Proper termination is shown in the Systems Applica- tions section. Twisted Pair Receivers RXD is a differential twisted-pair receiver. When prop- erly terminated, RXD will meet the electrical require- ments for 10BASE-T receivers as specified in IEEE 802.3, Section 14.3.1.3. The receivers do not require Am79C984A , 0-1 Pull Up/Pull Down ...
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... Bank A LEDs causes the LDA to be driven LOW, and Enable Software Override of Bank B LEDs causes the LDB driven LOW. The blink rate is set by the Software Over- ride LED Blink Rate command. The periods are off, 512 ms, 1560 ms, or solid on. Am79C984A , and 0-4 and LDB repre- 0-4 ...
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... The status port uses eight dedicated out- puts (ACT 0-7 LEDs in the series that will be lit increases as the amount of network activity increases. ACT the lowest level of activity; ACT est. ACT 0 current to turn on the LEDs. See Figure 2. Am79C984A AUI LEDs LDB LDA LDB 1-4 0 PAR LB ...
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... Activity Figure 2. Network Activity Display Number of LEDs Lit by ACT latch data; update display; clear counter next counting cycle counter is active Figure 3. Activity Sampling Am79C984A V DD 20650A-7 Table 3. Network Utilization Percentage Utilization 7-0 >80% >64% >32% >16% >8% >4% >2% >1% 20650B-8 19 ...
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... When ACK is HIGH, DAT and JAM are in the high- impedance state. DAT and JAM go active when ACK goes LOW. Refer to the Systems Applications section (Figure 13) for the configuration of IMR+ mode of operation. Note: The IMR+ mode is recommended when arbitrating between multiple boards. ))+ 0 . Am79C984A ...
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... If the latter method is used, 20 SCLK clock transi- tions are required for control commands that produce SO data, and 14 SCLK clock transitions are required for control commands that do not produce SO data. Am79C984A SELI_0 SELO SELI_1 20650A-10 ...
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... Programmable Option—S Off AUI Partitioning Algorithm TP Partitioning Algorithm AUI/TP Port Link Test Link Pulse Automatic Receiver Polarity Reversal Extended Distance Mode Blink Rate Software Override of LEDs Am79C984A 20650A-11 20650B-11 Normal Normal Enabled Enabled Enabled State reset Disabled Off ...
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... Am79C984A SO Data PBSL 0000 PBSL 0000 PBSL 0000 PBSL 0000 0000 C3..C0 0000 E3..E0 0000 L3..L0 0000 P3..P0 M000 0000 0000 0011 23 ...
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... Enable Link Pulse (Per TP Port) SI Data SO Data This command enables the transmission of the Link pulse on the TP port designated by the two least- significant bits of the command byte. Am79C984A 0011 1111 None 0010 00## None 0011 00## None ...
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... Software Override Blink Rate command. Enable Software Override of Bank A LEDs references the blink rate last issued and overrides any other attribute specified by LDC ride of LEDs is disabled after reset. Am79C984A 1001 #### None Port(s) affected AUI port ...
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... The response to this command gives the bit-rate-over- flow or underflow (data rate mismatch) condition of all the TP ports indicates that the FIFO has overflowed or underflowed due to the amount of data received by the corresponding port. Am79C984A 1000 1011 PBSL 0000 1000 1101 PBSL 0000 ...
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... IEEE 802.3, Section 14.4 specifi- cations. The cable is terminated at the opposite end by 100 . Twisted Pair Receivers RXD signals need to be properly terminated to meet the electrical requirements for 10BASE-T receivers. Proper termination is shown in Figure 9. Note that the receivers do not require external filter modules. Am79C984A 27 ...
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... RXD2– 1:1 TXD3+ 110 TXD3– 1:1 RXD3+ 100 RXD3– RST CLK Figure 7. Simplified 10BASE-T Connection 1:1 Figure 8. TXD Termination 1:1 Figure 9. RXD Termination Am79C984A TP Connector TP Connector TP Connector TP Connector 20650A-12 Twisted Pair 100 20650A-13 20650B-13 Twisted Pair 100 20650A-14 20650A-14 20650B-14 ...
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... The IMR+ mode maintains the full functionality of AMD’s IMR+ (Am79C981) device’s expansion bus. In this mode, the eIMR device requires external circuitry to The DAT and handle arbitration for control of the bus. Figure 12 shows the configuration for the IMR+ mode of operation. Am79C984A eIMR 1:1 DI+ DI– 40 ...
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... SELO CLK eIMR SELI_0 SELI_1 RST SELO CLK eIMR SELI_0 SELO SELI_1 DAT JAM ACK COL COL ACK SEL1 SEL2 SEL3 Arbiter Figure 12. IMR+ Mode External Arbitration Am79C984A eIMR SELI_0 SELI_1 RST SELO CLK 20650B-16 eIMR ...
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... LEDs. The open drain out- put of these drivers facilitate this configuration. Refer to Figure 13 LDA[4:0] LDB[4:0] LDA[4:0] LDB[4:0] Figure 13. Visual Status Display Connection Am79C984A VDD LDGA LDGB LDGA LDGB 20650B-18 20650A-19 31 ...
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... 5 – (Note (Note <V < (Note 5 Am79C984A ) . . . . . . . . . . . . . . . . . + Min Max Unit –0.5 0.8 V 2.0 0 – 0.4 V 2.4 – V – – – 0.4 V –500 500 A V – 3.0 V – ...
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... Sinusoid 5 MHz<f<10 MHz Sinusoid 5 MHz<f<10 MHz Sinusoid 5 MHz<f<10 MHz Sinusoid 5 MHz<f<10 MHz Sinusoid 5 MHz<f<10 MHz Sinusoid 5 MHz<f<10 MHz (Note 1) CLK = 20 MHz V = +5.25V DD CLK = 20 MHz V = +5.25V DD Am79C984A Min Max Unit 300 520 mV –520 –300 mV 150 293 mV –293 –150 mV 180 365 mV –365 –180 ...
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... IN ASQ |V |>|V | (Note 3) IN ASQ |V |>|V | (Note 4) IN ASQ |V |>|V | (Note 5) IN ASQ 100 100 pF L Am79C984A Min Max Unit 49.995 50.005 – – 150 – – – – ...
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... RXD pulses narrower than t PWKRD RXD carrier sense off Test Conditions |V |>|V | (Note 6) IN THS C = 100 pF L (min) will maintain internal RXD carrier sense on; a pulse wider than t Am79C984A Min Max – 50 250 375 136 200 120 100 – ...
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... Don’t Care, Any Change Permitted Does Not Apply t CLK t CLKH t CLKL t t CLKF CLKR Figure 14. Clock Timing Am79C984A OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State ...
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... AMODE, SELI_0 RST SCLKR t SCLK t t SCLKH SCLKL t SISET Figure 15. Control Port Timing t t RSTHLD t RST or t PRST Figure 16. Reset Timing t XRS Figure 17. Mode Initialization Am79C984A t SCLKF t SIHLD 20650B-20 20650A-21 RSTSET 20650B-21 20650A-22 t XRH 20650B-22 37 ...
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... TCLK SELO ACK COL DAT/JAM Note: TCLK represents internal eIMR timing DJSET IN Figure 18. Expansion Bus Input Timing t t CLKHRH CLKHRL t CASET t CAHLD t CLKHDR OUT Figure 19. Expansion Bus Output Timing Am79C984A t DJHOLD 20650B-23 t CASET t CLKHDZ 20650B-24 ...
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... PWKDI (t PWKCI DI+ ( ASQ t PWODI (t ) PWOCI CLKHRH t CLKHRL t CASET Figure 20. Expansion Bus Collision Timing t DOTR t Figure 21. AUI Timing Diagram ) Figure 22. AUI Receive Diagram Am79C984A t CASET t CAHLD IN 20650B-25 20650A-26 t DOETD DOTF 20650B-26 t PWKDI (t ) PWKCI 20650A-28 20650B-27 39 ...
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... TXETD Figure 23. TP Ports Output Timing Diagram t PERLP Figure 24. TP Idle Link Test Pulse t t PWKRD PWKRD Figure 25. TP Receive Timing Diagram Am79C984A 1 0 ETD t TXETD 20650A-29 20650B-28 t PWKRD V THS+ V THS– ...
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... SWITCHING TEST CIRCUIT Pin Test Point V SS Figure 26. Switching Test Circuit Am79C984A 20650A-32 20650B-31 41 ...
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... Pin 1 I.D. 1.185 1.195 1.150 1.156 .026 .050 REF .032 TOP VIEW .062 .083 .042 .056 .007 .013 .090 .130 .165 .180 SIDE VIEW Am79C984A 1.090 1.130 1.000 REF .013 .021 SEATING PLANE 16-038-SQ PL 084 DF79 8-1-95 ae ...
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... PHYSICAL DIMENSIONS PQR100 100-Pin Plastic Quad Flat Pack Pin 100 12.35 REF Pin 1 I.D. Pin 30 2.70 2.90 0.25 MIN 17.00 17.40 13.90 14.10 Pin 50 0.65 BASIC Am79C984A Pin 80 18.85 REF 19.90 20.10 23.00 23.40 3.35 MAX SEATING PLANE 16-038-PQR-2 PQR100 DA92 8-2- ...
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... Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am186, Am386, Am486, Am29000, b IMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet, PCnet- FAST , PCnet- FAST +, PCnet-Mobile, QFEX, QFEXr, QuASI , QuEST, QuIET, TAXIchip, TPEX, and TPEX Plus are trademarks of Advanced Micro Devices, Inc ...