am79c960 Advanced Micro Devices, am79c960 Datasheet
am79c960
Available stocks
Related parts for am79c960
am79c960 Summary of contents
Page 1
... PRELIMINARY Am79C960 TM PCnet -ISA Single-Chip Ethernet Controller DISTINCTIVE CHARACTERISTICS Single-chip Ethernet controller for the Industry Standard Architecture (ISA) and Extended Industry Standard Architecture (EISA) buses Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards Direct interface to the ISA or EISA bus Software compatible with AMD’s Am7990 ...
Page 2
... MAC. In addition, the device provides programmable on-chip LED drivers for transmit, receive, collision, receive polarity, link integ- rity, or jabber status. The PCnet-ISA controller also provides an External Address Detection Interface (EADI ) to allow external hardware address filtering in internetworking applications. (IMR+ ) (HIMIB ) (ILACC ) Am79C960 ...
Page 3
... K = Plastic Quad Flat Pack (PQR120) SPEED Not Applicable The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C960 AMD Valid Combinations 1-345 ...
Page 4
... Am79C960 1-343 ...
Page 5
... Am79C960 AMD 1-374 ...
Page 6
... Am79C960 1-388 ...
Page 7
... Am79C960 AMD 1-399 1-399 ...
Page 8
... Am79C960 1-411 ...
Page 9
... Am79C960 AMD 1-427 ...
Page 10
... MAC Core RCV Encoder/ FIFO Decoder (PLS) & AUI Port XMT FIFO 10BASE-T MAU FIFO Control Private Bus Control JTAG Port Control Am79C960 DXCVR MAUSEL/EAR CI+/- DI+/- XTAL1 XTAL2 DO+/- RXD+/- TXD+/- TXP+/- APCS BPCS LED0-3 PRDB0-7 TDO TMS TDI TCK 16907B-1 ...
Page 11
... DVSS4 17 SA2 18 SA3 SA4 19 20 DVSS10 21 SA5 SA6 22 SA7 23 24 SA8 25 DVSS5 26 SA9 27 SA10 28 SA11 29 DVDD3 30 SA12 Am79C960 AMD 90 XTAL2 89 AVSS2 XTAL1 88 AVDD3 87 TXD+ 86 TXP+ 85 TXD- 84 TXP AVDD4 81 RXD+ 80 RXD- 79 DVSS12 SD15 78 SD7 77 SD14 76 ...
Page 12
... DVSS11 82 AVDD4 AEN 83 TXP– IOCHRDY 84 TXD– RESET 85 TXP+ SLEEP 86 TXD+ IOAM0 87 AVDD3 IOAM1 88 XTAL1 DVDD5 89 AVSS2 SD0 90 XTAL2 Am79C960 Pin # Name 91 AVSS1 92 DO– 93 DO+ 94 AVDD1 95 DI– 96 DI+ 97 CI– 98 CI+ 99 AVDD2 100 DXCVR 101 MAUSEL/EAR LED3 102 ...
Page 13
... SA6 10 SA7 11 SA8 12 SA9 106 SA10 105 SA11 103 SA12 102 SA13 41 SA14 101 SA15 40 SA16 39 SA17 116 SA18 115 SA19 Am79C960 AMD Pin # Name Pin # SBHE 114 13 112 SD0 60 111 SD1 62 110 SD2 65 109 SD3 67 108 SD4 70 48 SD5 72 55 ...
Page 14
... System Memory Read Select Address PROM Chip Select Boot PROM Chip Select Disable Transceiver Input/Output Address Map LED0/LNKST LED1/SFBD/RCVACT LED2/SRD/RXPOL LED3/SRDCLK/XMTACT MAU SELect/External Address Reject PROM Data Bus Sleep Mode Test Enable Crystal Input Crystal Output Am79C960 I/O Driver TS3 I/O OD3 I/O OD3 OD3 ...
Page 15
... Transmit Data 10BASE-T Predistortion Control Test Clock Test Data Input Test Data Output Test Mode Select Analog Power Analog Ground Digital Power Digital Ground Table: Output Driver Types Type Iol (mA Am79C960 AMD I/O Driver TS2 I Ioh (mA) pF – ...
Page 16
... An attention signal which indicates that one or more of the following status flags is set: BABL, MISS, MERR, RINT, IDON, RCVCCO, JAB, MFCO, or TXSTRT. All Input/Output status flags have a mask bit which allows for suppression of INTR assertion. These flags have the fol- lowing meaning: Am79C960 Input/Output Input Input Output ...
Page 17
... I/O space, APCS is asserted. The outputs of the exter- nal Address PROM drive the PROM Data Bus. The Input PCnet-ISA controller buffers the contents of the PROM data bus and drives them on the lower eight bits of the System Data Bus. Am79C960 AMD Input Input/Output Input/Output Input/Output ...
Page 18
... Refer to the section on External Crystal Characteristics for more details. SF/BD XTAL2 SRD Crystal Connection SRDCLK The internal clock generator uses a 20 MHz crystal that is attached to pins XTAL1 and XTAL2 external clock is used, this pin should be left unconnected. Am79C960 Input Input Input Input . DD Input Output ...
Page 19
... MAC Core RCV Encoder/ FIFO Decoder (PLS) & AUI Port XMT FIFO 10BASE-T MAU FIFO Control Private Bus Control JTAG Port Control Am79C960 AMD DXCVR MAUSEL/EAR CI+/- DI+/- XTAL1 XTAL2 DO+/- RXD+/- TXD+/- TXP+/- ABOE APCS BPCS LED0-3 PRAB0-15 PRDB0-7 SROE SRWE TDO ...
Page 20
... DVSS4 17 PRAB2 18 PRAB3 PRAB4 19 20 DVSS10 21 PRAB5 PRAB6 22 PRAB7 23 24 PRAB8 25 DVSS5 26 PRAB9 27 PRAB10 28 PRAB11 29 DVDD3 30 PRAB12 1-362 Am79C960 90 XTAL2 89 AVSS2 XTAL1 88 AVDD3 87 TXD+ 86 TXP+ 85 TXD- 84 TXP AVDD4 81 RXD+ 80 RXD- 79 DVSS12 SD15 78 SD7 77 SD14 76 SD6 ...
Page 21
... DVSS11 82 AVDD4 AEN 83 TXP– IOCHRDY 84 TXD– RESET 85 TXP+ SLEEP 86 TXD+ IOAM0 87 AVDD3 IOAM1 88 XTAL1 DVDD5 89 AVSS2 SD0 90 XTAL2 Am79C960 AMD Pin # Name 91 AVSS1 92 DO– 93 DO+ 94 AVDD1 95 DI– 96 DI+ 97 CI– 98 CI+ 99 AVDD2 100 DXCVR 101 MAUSEL/EAR LED3 ...
Page 22
... RXD– 102 RXD+ 101 SA0 40 SA1 39 SA2 14 SA3 15 SA4 17 SA5 18 SA6 19 SA7 21 SA8 22 SA9 SBHE 23 24 SD0 26 SD1 Am79C960 Pin # Name Pin # 27 SD2 65 28 SD3 67 30 SD4 70 31 SD5 72 32 SD6 75 33 SD7 77 116 SD8 61 115 SD9 63 114 SD10 ...
Page 23
... MAU SELect/External Address Reject PRivate Address Bus PRivate Data Bus Sleep Mode Shared Memory Architecture Shared Memory Address Match Static RAM Output Enable Static RAM Write Enable Test Enable Crystal Oscillator Input Crystal Oscillator OUTPUT Am79C960 AMD I/O Driver I O OD3 I/O OD3 I I ...
Page 24
... Transmit Data 10BASE-T Predistortion Control Test Clock Test Data Input Test Data Output Test Mode Select Analog Power Analog Ground Digital Power Digital Ground Table: Output Driver Types Type Iol (mA Am79C960 I/O Driver TS2 I Ioh (mA) pF –1 50 – ...
Page 25
... PC/XT, SBHE will always be HIGH and the PCnet-ISA controller will perform only 8-bit op- erations. There must be at least one LOW going edge on Input this signal before the PCnet-ISA controller will perform 16-bit operations. Am79C960 AMD Output Babble Receive Collision Count Overflow Jabber ...
Page 26
... Private Address Bus The Private Address Bus is the address bus used to drive the Address PROM, Remote Boot PROM, and SRAM. PRAB10-15 are required to be buffered by a Bus Buffer with ABOE as its control and SA10-15 as its inputs. Am79C960 Input IOAM1,0 I/O Base 0 0 300 Hex ...
Page 27
... Refer to the section on External Crystal Characteristics for more details. XTAL2 Crystal Connection The internal clock generator uses a 20 MHz crystal that is attached to pins XTAL1 and XTAL2 external clock is used, this pin should be left unconnected. Am79C960 AMD Output Output Input . DD ...
Page 28
... TDO is tri-stated when JTAG port is inactive. TMS Test Mode Select Output This is a serial input bit stream used to define the spe- cific boundary scan test to be executed. unconnected, this pin has a default value of HIGH. Am79C960 Input Input Output Input If left ...
Page 29
... These pins are moderately quiet and should be connected to the VDD supply a short distance away from the DVDD pins. These pins are more noisy and should be connected to the DVDD/DVSS supplies. Am79C960 AMD Power Power ground reference to digital portions of Comments ...
Page 30
... Data buffers are located in motherboard memory and can be accessed by the PCnet-ISA controller when the device becomes the Current Master. 8-Bit Private Data PRDB0–7 APCS PCnet-ISA BPCS Controller Bus Master Block Diagram Am79C960 Ethernet D0–7 Address CS PROM A0–X D0–7 Boot CS PROM A0– ...
Page 31
... LOW on the pin will select the AUI interface. 16-Bit Private Address Bus PRAB0–15 8-Bit Private Data PRDB0–7 PCnet-ISA Controller APCS SROE BPCS SRWE Buffer Shared Memory Block Diagram Am79C960 AMD A0–X Ethernet Address CS PROM D0–7 A0–X 8-Bit D0–7 SRAM OE ...
Page 32
... STOP bit in CSR0, followed by writing to CSR15, and then setting the START bit in CSR0. Note that this form of restart will not perform the same in the PCnet-ISA controller as in the LANCE. In particular, the PCnet-ISA controller reloads the transmit and receive descriptor pointers with their respective base ad- Am79C960 ...
Page 33
... When transmit and receive functions begin, the base address of each ring is loaded into the current descriptor address registers and the address of the next descriptor entry in the transmit and receive rings is computed and loaded into the next descriptor address registers. Am79C960 AMD 1-375 ...
Page 34
... RMD1 and RMD0 of the current RDTE and TMD1 and TMD0 of the current TDTE at periodic polling intervals. All information collected during polling activity will be stored internally in the appropriate CSRs. (i.e. CSR18–19, CSR20–21, CSR40, CSR42, CSR50, CSR52). UnOWNed descriptor status will be internally ignored. Am79C960 • • • ...
Page 35
... PCnet-ISA controller in the transmit descriptor ring and, therefore, the condition is treated as a fatal error. To avoid this situation, the system should always set the transmit chain descriptor own bits in reverse order. Am79C960 AMD 1-377 ...
Page 36
... Receive data transfers to the second buffer may occur before the PCnet-ISA control- ler proceeds to look ahead to the ownership of the third buffer. Such action will depend upon the state of the FIFO when the status has been updated on the first de- Am79C960 ...
Page 37
... In addition, multiple physical ad- dresses can be constructed (perfect address filtering) using external logic in conjunction with the EADI interface. When Error Detection (Physical Medium Transmission Errors) The MAC engine provides several facilities which report and recover from errors on the medium. In addition, the Am79C960 AMD 1-379 ...
Page 38
... If the deference process simply times the interpacket gap based on this indica- tion it is possible for a short interFrame gap to be generated, leading to a potential reception failure of a subsequent frame. To enhance sys- tem robustness measures, as specified in 4.2.8, are recom- Am79C960 the following optional ...
Page 39
... In this case, only the RTRY bit will be set and the transmit message will be flushed from the FIFO collision is detected after 512 bit times have been transmitted, the collision is termed a late collision. The Am79C960 AMD s blinding window, then the IPG 1-381 ...
Page 40
... Manchester encoded serial bit stream. The transmit outputs (DO ) are de- signed to operate into terminated transmission lines. When operating into a 78 line, the transmit signaling meets the required output levels and skew for Cheapernet, Ethernet, and IEEE-802.3. Am79C960 Min Nom Max Units 20 MHz – ...
Page 41
... The Manchester “1” at bit 5 is clocked to IRXDAT output at 1/4 bit time in bit cell 6. Manchester Data Decoder Receiver Noise Carrier Reject Detect Filter Circuit Receiver Block Diagram Am79C960 AMD IRXDAT* ISRDCLK IRXCRS* 16907B-8 1-383 ...
Page 42
... When the signal is detected by the MENDEC it sets the ICLSN line HIGH. The condition continues for approximately 1.5 bit times after the last LOW-to-HIGH transition interface which Am79C960 1% resistors and IDF , are specified so ICM is the nearest usable ...
Page 43
... This definition is consistent with the expected received signal at a correctly wired receiver, when a link beat pulse, which fits the template of Figure 14-12 of the 10BASE-T Standard, is generated at a transmitter and passed through 100 m of twisted pair cable. Am79C960 AMD 1-385 ...
Page 44
... RXD pair. In snooze mode, the T-MAU receive circuitry will remain enabled even while the SLEEP pin is driven LOW. The T-MAU circuitry will always go into power down mode if RESET is asserted, coma mode is enabled, or the T-MAU is not selected. Am79C960 ...
Page 45
... ISA bus driver circuits. However, external circuitry could still re- spond to specific frames on the network to facilitate remote node control. The table below summarizes the operation of the EADI features. Required Timing Am79C960 AMD Received Messages All Received Frames All Received Frames Physical/Logical Matches 1-387 ...
Page 46
... LA[22–23] will be outputs. Table: GPSI Pin Configurations LANCE/ PCnet-ISA C-LANCE GPSI GPSI Pin Pin Function RX RXDAT RCLK SRDCLK RENA RXCRS CLSN CLSN TCLK STDCLK TENA TXEN TX TXDAT Am79C960 PCnet-ISA Pin PCnet-ISA Normal Number Pin Function 5 LA17 6 LA18 7 LA19 9 LA20 10 LA21 11 LA22 12 LA23 ...
Page 47
... Bits 11–1: Manufacturer ID. The 11 bit manufacturer ID code for AMD is 00000000001 according to JEDEC Publication 106-A. Bit 0: Always a logic 1 Selected Data Reg BSR ID REG BSR Bypass Bypass Bypass Am79C960 AMD Capture Shift Update System Function Instruction Mode Code Test 0000 Normal 0001 Normal 0010 ...
Page 48
... PCnet-ISA controller asserts MEMCS16 when either of the two memory resources is selected. The ISA bus re- quires that all memory resources within a block of 128 Kbytes be the same width, either 8- or 16-bits. The reason for this is that the MEMCS16 signal is generally a decode of the LA 17-23 Am79C960 address lines. 16-bit memory ...
Page 49
... Slave x Master Float 1 Float* Master 1 Master Master 0 Float Master 0 Master Master Am79C960 AMD Comments Low byte RD High byte RD with swap 16-Bit RD converted to low byte RD High byte RD 16-Bit RD Low byte WR High byte WR with swap 16-Bit WR converted to low byte WR High byte WR 16-Bit WR 1-391 ...
Page 50
... BPCS signal from the PCnet-ISA controller. This signal is intended to be connected to the CS pin on the boot PROM, with the PROM OE pin tied to ground. When us- ing a PROM with an access time slower than 120 ns, BPCS may be connected to the OE pin of the boot PROM while tying the PROM CS pin to ground. Am79C960 ...
Page 51
... ISACSR2 is set. The EISA bus requires all command lines to remain inactive for at least 170 ns before starting another bus cycle. When bit 4 in ISACSR4 is cleared, the PCnet-ISA con- troller provides 200 ns of inactive time. Am79C960 AMD 1-393 ...
Page 52
... ISA memory bus cycles only. Since this is an illegal situation for simple address decoders, the exter- nal address decoder must artificially drive SMAM LOW when the (8-bit) boot PROM address space is being ac- cessed. In this case, MEMCS16 must not be asserted. Am79C960 ...
Page 53
... MEMCS16 and SBHE signals do not exist in the PC/XT environment. At the memory device level, each SRAM Private Bus read cycle takes two 50 ns clock periods for a maximum read access time of 75 ns. The timing looks like this: 16907B-10 Static RAM Read Cycle Am79C960 AMD 1-395 ...
Page 54
... The default value of APAD_XMT is 0, and this will disable auto pad generation after RESET. Dest Srce Length ADDR ADDR Bytes Bytes Bytes ISO 8802–3 (IEEE/ANSI 802.3) Data Frame Am79C960 LLC Pad FCS Data 4 Bytes 46-1500 Bytes 16907B-12 ...
Page 55
... Manchester Encoder/Decoder will expect the SQE Test Message (nominal 10 MHz sequence re- turned via the CI pair within a 40 network bit time period after DI pair goes inactive. If the CI inputs are not asserted within the 40 network bit time period following Am79C960 AMD pair is 1-397 ...
Page 56
... Bytes Bytes Bytes Dest Srce Length ADDR ADDR Bit Bit Bit Most Significant Significant Byte Am79C960 46–1500 Bytes 4 Bytes LLC Pad FCS DATA 1–1500 45–0 Bytes Bytes Bit 7 Least Byte 16907B-13 ...
Page 57
... TPEX (Am79C98) and TPEX+ (Am79C100) LED outputs. Signal LNKST Active during Link OK Not active during Link Down RCV Active while receiving data RVPOL Active during receive polarity is OK Not active during reverse receive polarity XMT Active while transmitting data Am79C960 AMD Behavior 1-399 ...
Page 58
... Hz. The data input of the shift register is at logic 0. The OR gate output asynchronously sets all three bits of the shift register when its output goes active. The output of the shift register controls the associated LEDx pin. Thus, the pulse stretcher provides an LED output ms. 16907B-14 Am79C960 ...
Page 59
... Writing a “0” has no effect. BABL is cleared CERR 12 MISS 11 MERR Am79C960 AMD by RESET or by setting the STOP bit. Collision Error indicates that the collision inputs to the AUI port failed to activate within 20 net- work bit ...
Page 60
... RXON 4 TXON 3 TDMD block from Unit after the Am79C960 and INTR is set, IRQ will be active. INTR is cleared automatically when the condition that caused interrupt is cleared. INTR is read only. INTR is cleared by RESET or by setting the STOP bit. Interrupt Enable allows IRQ to be active if the Interrupt Flag is set. If IENA = “ ...
Page 61
... MERRM 10 RINTM 9 TINTM accessible only 8 IDONM 7-5 RES Am79C960 AMD Upper 8 bits of the address of the Initialization Block. Bit locations 15-8 must be written with zeros. Whenever this register is written, CSR17 is updated with CSR2’s contents. Read/Write accessible only when the STOP bit in CSR0 is set. Unaffected by RESET. ...
Page 62
... RCVCCOM Polling. If will disable 3 TXSTRT Am79C960 DPOLL is cleared by RESET. Auto Pad Transmit. When set, APAD_XMT enables the auto- matic padding feature. Transmit frames will be padded to extend them to 64 bytes, including FCS. The FCS is calculated for the en- tire frame (including pad) and appended after the pad field ...
Page 63
... CSR10: Logical Address Filter, LADRF[47:32] Bit Name 15-0 LADRF[47:32] Logical CSR11: Logical Address Filter, LADRF[63:48] Bit Name 15-0 LADRF[63:48] Logical Am79C960 AMD Read accessible only when STOP bit is set. Write operations have no effect and should not be performed. RLEN is only defined after initialization. Reserved locations. Read as zero ...
Page 64
... DRCVPA Register, 12 DLNKTST Register, 11 DAPC 10 MENDECL 9 LRT/TSEL Am79C960 Promiscuous Mode. When PROM = “1”, all incoming receive frames are accepted. Read/write accessible only when STOP bit is set. DisableReceive Broadcast When . set, disables the PCnet-ISA con- troller from responding to broad- cast messages. Used for proto- ...
Page 65
... General Purpose Serial Interface for detailed information on accessing GPSI. 6 INTL 10BASE-T 5 DRTY of the unsquelch 4 FCOLL 3 DXMTFCS the Am79C960 AMD Network Port 0 0 AUI 0 1 10BASE GPSI Reserved Internal Loopback. See the de- scription of LOOP, CSR15.2. Read/write accessible only when STOP bit is set. ...
Page 66
... RES 23-0 CXBA CSR22-23: Next Receive Buffer Address Bit Name 31-24 RES 23-0 NRBA Am79C960 is an alias of CSR1. Whenever this register is written, CSR1 is updated with CSR16’s contents. Read/Write accessible only when the STOP bit in CSR0 is set. Unaffected by RESET. Description Reserved locations. Written as zero and read as undefined. ...
Page 67
... CSR38-39: Next Next Transmit Descriptor Address Bit Name 31-0 NNXDA CSR40-41: Current Receive Status and Byte Count Bit Name 31-24 CRST Am79C960 AMD Description Reserved locations. Written as zero and read as undefined. Contains the next TDRE address pointer. Read/write accessible only when STOP bit is set. Description Reserved locations ...
Page 68
... Bit Name 31-16 RES 15-0 POLLINT CSR48-49: Temporary Storage Bit Name 31-0 TMP0 Am79C960 to trigger the descriptor ring poll- ing operation of the PCnet-ISA controller. Read/write accessible only when STOP bit is set. Description Reserved locations. Written as zero and read as undefined. Polling Interval. This register contains ...
Page 69
... NXBA CSR66-67: Next Transmit Status and Byte Count Bit Name 31-24 NXST 23-12 RES 11-0 NXBC Am79C960 AMD Description Previous Transmit Status. This field is a copy of bits 15:8 of TMD1 of the previous transmit descriptor. Read/write accessible only when STOP bit is set. Reserved locations. Written as zero and read as undefined. ...
Page 70
... XMTRL CSR80: Burst and FIFO Threshold Control Bit Name 15-14 RES 13-12RCVFW[1:0] Am79C960 value in the RLEN field of the initialization block. This register can be manually altered; the ac- tual receive ring length is defined by the current value in this register. Read/write accessible only when STOP bit is set. ...
Page 71
... FIFO Watermark. DMA stops, Read/write Write Cycles Reserved Am79C960 AMD DMA Burst Register. This regis- ter contains the maximum allowable number of transfers to system memory that the Bus In- terface will perform during a single DMA cycle. The Burst Register is not used to limit the ...
Page 72
... CSR94:Transmit Time Domain Reflectometry Count Bit Name 15-10 RES 9-0 XMTTDR Am79C960 (CSR4.15) is asserted, all writes to this register will automatically perform an increment cycle. Read/write accessible only when STOP bit is set. Description Version. This 4-bit pattern is sili- con revision dependent. Part number. The 16-bit code for ...
Page 73
... CSR124: Buffer Management Unit Test SWAP[15:0] Bit Name SWAP[31:16] SWAP SWAP[15:8] Am79C960 AMD Description The Buffer Management Scratch register is used for assembling Receive and Transmit Status. This register is also used as the primary scan register for Buffer Management Test Modes ...
Page 74
... Link Integrity Default: RCV Default: RCVPOL Default: XMT 6-5 RES 4 ISAINACT Am79C960 active. The default value of 5h in- dicates 250 ns pulse widths. A value will generate 50 ns wide commands. Description Reserved locations. Written as zero and read as undefined. This register is used to tune the MEMW command signal active time ...
Page 75
... PSE 6-5 RES 4 XMT E 3 RVPOL E 2 RCV E 1 JAB E 0 COL E Am79C960 AMD Link Status LED is asserted, indi- cating good 10BASE-T integrity. Reserved locations. Written as 0, read as undefined. Description ISACSR5 controls the func- LED1 tion(s) that the pin displays. Multiple functions can be simultaneously enabled on this LED pin ...
Page 76
... PSE 6-5 RES 4 XMT E 3 RVPOL E 2 RCV E 1 JAB E 0 COL E Am79C960 Description ISACSR7 controls the func- LED3 tion(s) that the pin displays. Multiple functions can be simultaneously enabled on this LED pin. The LED display will indicate the logical OR of the en- abled functions ...
Page 77
... A logical address is passed through the CRC generator, producing a 32-bit result. The high order 6 bits of the CRC are used to select one of the 64 bit positions in the Logical Address Filter. If the selected filter bit is set, the address is accepted and the frame is placed into memory. Am79C960 AMD # of DREs 000 1 001 ...
Page 78
... RMD0 Holds LADR [15:0]. This is combined with HADR [7:0] in RMD1 to form the 24-bit address of the buffer pointed to by this descriptor table entry. There are no restrictions on buffer byte alignment or length. RMD1 Bit Name 15 OWN Am79C960 32-Bit Resultant CRC 0 26 Logical Address Filter (LADRF ...
Page 79
... The length of the message buffer. Status information indicating the condition of the buffer. The eight most significant bits of TMD1 (TMD1[15:8]) are collectively termed the STATUS of the transmit descriptor. Am79C960 AMD END OF PACKET indicates that this is the last buffer used by the PCnet-ISA controller for this frame ...
Page 80
... TMD2 Bit Name 15-12 ONES 11-0 BCNT Am79C960 has meaning only if the ENP or the ERR bit is set. DEFERRED indicates that the PCnet-ISA controller had to defer while trying to transmit a frame. This condition occurs if the chan- nel is busy when the PCnet-ISA controller is ready to transmit. ...
Page 81
... RTRY 09-00 TDR ERROR indi- Am79C960 AMD LATE COLLISION indicates that a collision has occurred after the slot time of the channel has elapsed. The PCnet-ISA control- ler does not re-try on late collisions. LCOL is written by the PCnet-ISA controller. LOSS OF CARRIER is set when ...
Page 82
... Polling Interval 32-bit TMP0: Temporary Storage 32-bit TMP1: Temporary Storage 32-bit TMP2: Temporary Storage 32-bit TMP3: Temporary Storage 32-bit TMP4: Temporary Storage 32-bit TMP5: Temporary Storage 32-bit PXDA: Previous XMT Descriptor Address 32-bit PXBC: Previous XMT Status and Byte Count Am79C960 Comments ...
Page 83
... XMTTDR: Transmit Time Domain Reflectometry 32-bit SCR0: BIU Scratch Register 0 32-bit SCR1: BIU Scratch Register 1 32-bit SWAP:16-bit word/byte Swap Register 32-bit BMSCR: BMU Scratch Register 16-bit Y Missed Frame Count 16-bit Y Receive Collision Count 16-bit Y BMU Test Register 16-bit Reserved Am79C960 AMD Comments 1-425 ...
Page 84
... Default 0005H Master Mode Read Active 0005H Master Mode Write Active 0002H Miscellaneous Configuration N/A Reserved for future AMD use LED0 Status (Link Integrity) 0000H LED1 Status (Default: RCV) 0084H LED2 Status (Default: RCVPOL) 0008H LED3 Status (Default: XMT) 0090H Am79C960 Name ...
Page 85
... To operate in an 8–bit PC/XT environment, the LA signals should have weak pull-down resistors con- nected to them to present a logic 0 level when not driven. 8-Bit Private Data PRDB0–7 APCS PCnet-ISA BPCS Controller Bus Master Block Diagram Am79C960 AMD Ethernet D0–7 Address CS PROM A0–X D0–7 Boot ...
Page 86
... Refer to the PCnet-ISA Technical Manual (PID #16850B) for network interface design and refer to Appendix A for a list of compatible AUI isolation transformers. 16907B-17 Am79C960 A0–X Ethernet Address CS PROM D0–7 A0–X 8-Bit D0– ...
Page 87
... Technical Manual (PID #18216A) for more design de- tails, and refer to Appendix A for a list of compatible 10BASE-T filter/transformer modules. Filter & Transformer Module 61.9 422.0 XMT 1.21 K 61.9 Filter 422.0 RCV 100 Filter Am79C960 AMD RJ45 Connector 1:1 TD+ 1 TD- 2 1:1 RD+ 3 RD- 6 16907A-018A 16907B-18 1-429 ...
Page 88
... External Clock IN Active Sleep Active IN DD Sleep AV < V < < V < (Note 5) L Am79C960 ) . . . . . . . . . . . . . . . . . + – – 0 Min Max 0.8 2 0.5 DD 0.5 2.4 –10 10 –10 10 –0.5 ...
Page 89
... Sinusoid 5 MHz f 10 MHz Sinusoid 5 MHz f 10 MHz –520 Sinusoid 5 MHz f 10 MHz Sinusoid 5 MHz f 10 MHz –293 LRT = 1 (Note 6) LRT = 1 (Note 6) –312 LRT = 1 (Note 6) LRT = 1 (Note 6) –156 Am79C960 AMD Max Unit – 2 – –160 mV +1.5 V –3.0 AV – ...
Page 90
... (Note 5) (Note 2 – =5.5V 2. 0.4V < V < V OUT DD XTAL1 = 20 MHz SLEEP active Awake bit set active Am79C960 Max Unit – –40 +40 mV –40 + 0.8 V 2.0 V 0.4 V 2.4 V –200 A – ...
Page 91
... DACK t DRQ to MMA2 DACK Inactive t MMA3 DACK to MASTER t MMA4 MASTER to Active Command, t MMA5 SBHE, SA0–19, LA17– Test Conditions IOW IOR IOCS16 Am79C960 AMD Min Max Unit 100 ...
Page 92
... MMR10 MEMR t SD Hold After MMR11 1-434 Test Conditions DRQ (Note 1) (Note 2) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 2) (Note 1) (Note 1) Am79C960 Min Max Unit – EXTIME + 45 EXTIME + 65 ns MSWRA – 10 MSWRA + 5 ...
Page 93
... EXTIME is 100 ns when ISACSR2, bit 4, is cleared (default). EXTIME when ISACSR2, bit 4, is set. 2. MSRDA and MSWDA are parameters which are defined in registers ISACSR0 and ISACSR1, respectively Test Conditions Min 125 140 125 140 Am79C960 AMD Max Unit 260 ns 155 ns 20 ...
Page 94
... MW5 MEMW t SD Hold After MW6 t IOCHRDY Delay From MW7 MEMW t IOCHRDY Inactive MW8 MEMW to t IOCHRDY MW9 1-436 Test Conditions IOW IOR Am79C960 Min Max Unit 150 125 ns ...
Page 95
... AEN, SBHE, SA0–9 to IOCS16 t IOCS2 tristated SRAM Read/Write, Boot PROM Read, Address PROM Read on Private Bus ABOE to PRAB10–15 Tristated t PR1 ABOE to PRAB10–15 t PR2 Active (Driven by Am79C960) t PRAB10–15 Inactive to PR3 t PRAB Change to PRAB PR4 Change, SRAM Access t PRDB Setup to PRAB PR5 ...
Page 96
... Change, BPROM Access t PRAB Change to PRAB PR13 Change, SRAM Write SRWE t PRAB Change to PR14 SRWE t PRAB Change to PR15 1-438 Test Conditions Min 145 145 120 Am79C960 Max Unit 155 155 130 ns ...
Page 97
... TCK JTG7 t TDO Tristate After TCK JTG8 Note: JTAG logic is reset with an internal Power-On Reset circuit independent of Sleep Modes Test Conditions Min –15 110 Test Conditions Min Am79C960 AMD Max Unit + 51,090 ns ...
Page 98
... Late Receive Collision. 1-440 Test Conditions TCLK TCLK (Last Bit) TENA (Note 1) (Note 2) (Note 2) (Note 2) RCLK RCLK RCLK (Note 3) RCLK for RCLK RCLK Am79C960 Min Max Unit 99.99 100. 210 110 ...
Page 99
... V = External Clock External Clock External Clock External Clock External Clock IN (max) will turn internal DI carrier sense on. PWODI (max) will turn internal CI carrier sense on. PWOCI Am79C960 AMD Min Max Unit 2.5 5.0 ns 2.5 5.0 ns 1.0 ns 200 375 136 ...
Page 100
... RXD Pulse Width to Turn Off PWROFF Note: 1. Not tested; parameter guaranteed by characterization. 1-442 Test Conditions Min (10% to 90%) (90% to 10%) (Note 1) (Note 1) VIN > VTHS (min) VIN > VTHS (min) Am79C960 Max Unit 250 350 ns 5 ...
Page 101
... May Change from Don’t Care Any Change Permitted Does Not Apply 16907B-19 Normal and Three-State Outputs Am79C960 OUTPUTS Will Be Steady Will Be Changing from Will Be Changing from Changing State Unknown Center Line is High Impedance “Off” State ...
Page 102
... 52.3 TEST POINT 154 100 16907B-20 AUI DO Switching Test Circuit DV DD 294 TEST POINT 294 100 16907B-21 TXD Switching Test Circuit DV DD 715 TEST POINT 715 100 16907B-22 TXP Outputs Test Circuit Am79C960 ...
Page 103
... AEN, SBHE, SA0–9 IOW IOCHRDY Stable t IOW1 t IOW3 t IOW5 I/O Write without Wait States Stable t IOW1 IOW7 IOW8 IOW9 t IOW5 I/O Write with Wait States Am79C960 AMD t IOW2 t IOW4 t IOW6 16907B-23 t IOW2 t IOW4 t IOW6 16907B-24 1-445 ...
Page 104
... IOR SD AEN, SBHE, SA0–9 IOR IOCHRDY SD 1-446 Stable t IOR1 t IOR5 Stable I/O Read without Wait States Stable t IOR1 t t IOR6 IOR7 t IOR8 Stable I/O Read with Wait States Am79C960 t IOR2 t IOR3 t IOR4 16907B-25 t IOR2 t IOR3 t IOR4 16907B-26 ...
Page 105
... SA0–9 IOCS16 REF DRQ t DACK t MMA3 MASTER MEMR/MEMW SBHE, SA0–19, LA17– IOM1 I/O to Memory Command Inactive Time t IOCS1 IOCS16 Timings t MMA1 MMA2 t MMA4 Bus Acquisition Am79C960 t IOM2 t IOCS2 t MMA5 AMD 16907B-27 16907B-28 16907B-29 1-447 ...
Page 106
... LA17–23 t MMW1 MEMW IOCHRDY t MMW10 SD0–15 1-448 MMBR1 MMBR2 t MMBR3 t MMBR4 Bus Release t t MMW5 MMW6 t t MMW2 MMW3 t MMW7 t MMW11 Write Cycles Am79C960 16907B-30 (Wait States Added) t MMW4 t t MMW8 MMW9 16907B-31 ...
Page 107
... MMR5 MMR6 Stable t t MMR2 MMR3 t t MMR10 MMR11 Stable Read Cycles Stable t IOR1 t IOR6 t MA1 t MA2 t MA3 Address PROM Read Cycle Am79C960 AMD (Wait States Added) Stable t MMR4 MMR7 MMR8 MMR9 t t MMR10 MMR11 Stable 16907B-32 t IOR2 t IOR3 t MA5 t ...
Page 108
... SWITCHING WAVEFORMS: BUS MASTER MODE REF, SBHE, SA0–19 SMEMR IOCHRDY BPCS PRDB0–7 SD0–7 1-450 Stable t MB1 t MB3 t MB5 t MB6 t MB8 Boot PROM Read Cycle Am79C960 t MB2 t MB4 t MB7 t MB9 t t MB10 MB11 Stable 16907B-34 ...
Page 109
... IOW IOCHRDY Stable t t IOW1 IOW3 I/O Write without Wait States Stable IOW1 t t IOW7 IOW8 t IOW9 I/O Write with Wait States Am79C960 AMD t IOW2 t IOW4 t t IOW5 IOW6 16907B-35 t IOW2 t IOW4 t t IOW5 IOW6 16907B-36 1-451 ...
Page 110
... SA0–9 IOR SD AEN, SBHE, SA0–9 IOR IOCHRDY SD 1-452 Stable t IOR1 t IOR5 Stable I/O Read without Wait States Stable t IOR1 t IOR6 t IOR7 t IOR8 I/O Read with Wait States Am79C960 t IOR2 t IOR3 t IOR4 16907B-37 t IOR2 t IOR3 t IOR4 Stable 16907B-38 ...
Page 111
... SM_AM t MEMW IOCHRDY Stable t t MW1 MW3 Memory Write without Wait States Stable MW1 t t MW7 MW8 Memory Write with Wait States Am79C960 AMD t MW2 t MW4 t t MW5 MW6 16907B-39 t MW2 t MW4 t MW9 t t MW5 ...
Page 112
... PRAB10–15, SBHE SMAM/BPAM MEMR IOCHRDY SD 1-454 Stable t MR1 t MR5 Stable Memory Read without Wait States Stable t MR1 t t MR6 MR7 t MR8 Memory Read with Wait States Am79C960 t MR2 t MR3 t MR4 16907B-41 t MR2 t MR3 t MR4 Stable 16907B-42 ...
Page 113
... SWITCHING WAVEFORMS: SHARED MEMORY MODE IOW, MEMW SMEMR, MEMR, IOR AEN, SBHE, SA0–9 IOCS16 IOM1 I/O to Memory Command Inactive Time t IOCS1 IOCS16 Timings Am79C960 AMD t IOM2 16907B-43 t IOCS2 16907B-44 1-455 ...
Page 114
... PR2 PRAB10–15 PRAB0–9 SROE PRDB 1-456 PR13 t PR14 t PR15 SRAM Write on Private Bus t PR4 t t PR5 PR6 SRAM Read on Private Bus Am79C960 t PR3 t PR13 t PR14 t PR15 16907B-45 t PR3 t PR4 t t PR5 PR6 16907B-46 ...
Page 115
... PRAB0–9 APCS PRDB PR10 t t PR11 PR12 Boot PROM Read on Private Bus t PR1 t PR2 t PR7 Address PROM Read on Private Bus Am79C960 AMD t PR3 t PR10 t t PR11 PR12 16907B-47 t PR3 t t PR8 PR9 16907B-48 1-457 ...
Page 116
... Collision (CLSN), Inactive 1-458 tGPT4 tGPT9 tGPT7 Transmit Timing (Address Type Designation Bit) (Last Bit) tGPR2 tGPR3 tGPR7 (No Collision) Receive Timing Am79C960 (Last Bit ) tGPT3 tGPT5 tGPT6 tGPT8 tGPR5 tGPR6 tGPR8 tGPR9 tGPR10 tGPR12 16907B-63 16907B-64 ...
Page 117
... Preamble SFD Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 t EAD3 t EAD5 EADI Reject Timing t JTG1 t JTG2 t JTG6 Test Access Port Timing Am79C960 AMD Data Field Bit 8 Bit 0 Bit 7 Bit 8 t EAD3 Accept Reject t EAD6 t t JTG7 JTG8 16907B-49 ...
Page 118
... Internal signal and is shown for clarification only. Transmit Timing—End of Packet (Last Bit = 0) 1-460 DOTR 1 Transmit Timing—Start of Packet Bit (n–1) Bit (n) Am79C960 t X1H t X1L t t X1F X1R DOTF 16907B-51 t DOETD Typical > ...
Page 119
... ITXEN (Note ITXDAT+ (Note 1) DO+ DO– Bit (n–2) Note: 1. Internal signal and is shown for clarification only. Transmit Timing—End of Packet (Last Bit = Bit (n–1) Bit (n) Am79C960 t DOETD Typical > 250 ns 16907B-53 AMD 1-461 ...
Page 120
... AMD SWITCHING WAVEFORMS: AUI DI+/– V ASQ t PWKDI t PWODI CI+/– V ASQ t PWOCI DO+/– 1-462 Receive Timing Diagram t PWKCI Collision Timing Diagram t DOETD 40 mV 100 mV max. 80 Bit Times Port DO ETD Waveform Am79C960 t PWKDI 16907B-54 t PWKCI 16907B- 16907B-56 ...
Page 121
... SWITCHING WAVEFORMS: 10BASE-T INTERFACE TXD+ TXP+ TXD– TXP– XMT t PWPLP TXD+ TXP+ TXD– TXP– t PWLP Transmit Timing t PERLP Idle Link Test Pulse Am79C960 AMD t TETD 16907B-57 16907B-60 1-463 ...
Page 122
... AMD SWITCHING WAVEFORMS: 10BASE-T INTERFACE RXD RXD 1-464 Receive Thresholds (LRT = 0; CSR15[9]) Receive Thresholds (LRT = 1; CSR15[9]) Am79C960 V TSQ+ V THS+ V THS– V TSQ– 16907B-61 V LTSQ+ V LTHS+ V LTHS– V LTSQ– 16907B-62 ...
Page 123
... TG01-0756W 16-pin 0.3” SMD EP9531-4 16-pin 0.3” DIL PE64106 16-pin 0.3” DIL PE65723 16-pin 0.3” SMT LT6032 16-pin 0.3” DIL ST7032 16-pin 0.3” SMD Am79C960 Filters Filters Filters Transformers Transformers Transformers and Choke Dual Chokes Dual Chokes Description ...
Page 124
... Am79C960 Voltage Remote On/Off 5/-9 No 5/-9 Yes 5/-9 No 5/-9 Yes 5/-9 Yes 5/-9 No 5/-9 Yes Europe 33-1-69410402 33-1-69413320 ...
Page 125
... VCO, AMD strongly recommends that the low-pass filter shown below be implemented on these pins. Tests us- ing this filter have shown significantly increased noise immunity and reduced Bit Error Rate (BER) statistics in designs using the PCnet-ISA controller. Am79C960 PCnet-ISA B-1 ...
Page 126
... To minimize the B-2 voltage drop across the resistor, the R value should not be more than AVSS2 and AVDD2/AVDD4 These pins provide power and ground for the AUI and twisted pair receive circuitry. No specific decoupling has been necessary on these pins. Am79C960 ...
Page 127
... CSR8 CSR9 CSR10 CSR11 CSR12 CSR13 CSR14 CSR15 CSR24-25 CSR30-31 CSR47 CSR76 CSR78 Note: The INIT bit must not be set or the initialization block will be accessed instead. Comment LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] PADR[15:0] PADR[31:16] PADR[47:32] Mode BADR BADX POLLINT RCVRL XMTRL Am79C960 C-1 ...