am79c930 Advanced Micro Devices, am79c930 Datasheet
am79c930
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am79c930 Summary of contents
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... Kbytes of non-volatile memory for MAC control code, PCMCIA configuration GENERAL DESCRIPTION PCnet-Mobile (Am79C930) is the first in a series of mo- bile networking products in AMD’s PCnet family. The Am79C930 device is the first single-chip wireless LAN media access controller (MAC) supporting the IEEE 802.11 (draft) standard and the Xircom Netwave™ ...
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... V = 144-Pin Thin Quad Flat Pack (PQT144) SPEED Not Applicable Valid combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C930 Valid Combinations ...
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... CA16–8 CAD 7–0 DRQ0 INT1 DRQ1 MAC ALE INT0 Control Unit (80188 core) WR SRDY UCS LCS RESET Am79C930 TRST JTAG TMS/T3 Control TDI/T1 Block TDO/T2 RXCIN ANTSLT ANTSLT SAR6–0 ADIN2–1 ADREF RXDATA RXC SDCLK ...
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... SIR7 Slave Control PCMCIA and ISA Memory and I/O PCMCIA Config Registers Plug and Play Control Module 80188 ISA Memory Base Interrupt Generator ISA I/O Base Am79C930 CA16 Latch ALE CA15–8 CAD7–0 MIR0 MIR1 ... MIR15 MOE MWE Slave Control UCS and ...
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... Transceiver Interface Unit Control TCR0 TX TCR... FIFO TCR31 8 Bytes P->S MUX MUX ÷80 BIAS Suppress ÷ ÷5 Sleep X ÷10 ÷20 Am79C930 Transceiver Control Signals RX FIFO 15 Bytes S-> FDET SFD Detect Count Phylen RXD TXD TXC RXC 20183B-3 5 ...
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... Am79C930 1 ...
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... Am79C930 AMD ...
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... TX Power Ramp Control Am79C930-based TX Power Ramp Control . Transceiver-Based TX Power Ramp Control . ...
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... Am79C930 AMD ...
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... Am79C930 95 ...
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... DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 V Am79C930 DC Characteristics 3.3 V Am79C930 DC Characteristics IEEE 1149.1 DC Characteristics (5.0 and 3.3 V) ...
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... V NON-PCMCIA AC Test Reference Waveform PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPENDIX A: Typical Am79C930 System Application Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... MD2 30 MD3 31 VSSM 32 MD4 33 MD5 34 MD6 35 MD7 36 Notes: Pin 1 is marked for orientation Connection Am79C930 Am79C930 108 SAR0 SDSEL1 107 VSST 106 SDSEL2 105 VDDT 104 SDSEL3 103 ADDATA 102 SDCLK 101 LNK 100 VSST ...
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... IOWR 102 SDDATA IORD 103 SDSEL3 A9 104 VDDT A11 105 SDSEL2 OE 106 VSST A10 107 SDSEL1 CE1 108 SAR0 Am79C930 Pin No. Pin Name 109 SAR1 110 SAR2 111 SAR3 112 SAR4 113 SAR5 114 SAR6 115 TXC 116 VSST 117 LFCLK ...
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... SDCLK 22 SDDATA 20 SDSEL1 19 SDSEL2 18 SDSEL3 9 STSCHG 8 TCK 27 TDI 28 TDO 30 TEST 31 TMS 33 TRST 34 TXC 35 TXCMD 36 TXCMD 38 TXDATA 11 TXDATA Am79C930 Pin Name Pin No. 70 TXMOD 131 79 TXPE 129 83 USER0 90 82 USER1 91 133 USER2 1 48 USER3 2 58 USER4 3 94 USER5 96 124 USER6 95 123 V 17 ...
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... PCMCIA interface SRAM Chip Enable—this signal becomes asserted when the SRAM device 1 SCE has been addressed by either the 80188 core of the Am79C930 device or by the software through the PCMCIA interface eXtra Chip Enable—this signal becomes asserted when the extra peripheral 1 ...
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... Test Reset—this is the reset signal for IEEE 1149.1 testing 1 USER7 User-programmable pin 1 RXC Receive Clock—provides decode receive clock Test pin—when asserted, this pin places the Am79C930 device into a 1 TEST nonstandard factory-only test mode Clock input to drive BIU, 80188 core, and TAI, supplying network data rate 1 CLKIN ...
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... Input with internal pulldown device Pin Function Type Type Size of Pullup Am79C930 Pin Style TS1 I I PTS3, PTS1 I Load OL OH – – –4 mA 120 pF – – ...
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... CA16–18 CAD 7–0 DRQ0 IEEE INT1 DRQ1 802.11 MAC ALE INT0 Control Unit (80188 core) WR RESET SRDY UCS LCS RESET Am79C930 TRST JTAG TMS/T3 Control TDI/T1 Block TDO/T2 RXCIN ANTSLT ANTSLT SAR6–0 ADIN2–1 ADREF RXDATA RXC SDCLK IEEE SDDATA 802 ...
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... MD3 31 VSSM 32 MD4 33 34 MD5 MD6 35 MD7 36 Notes: Pin 1 is marked for orientation Connection Am79C930 Am79C930 SAR0 108 SDSEL1 107 VSST 106 SDSEL2 105 VDDT 104 SDSEL3 103 ADDATA 102 SDCLK 101 LNK 100 ...
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... SDDATA IOR 103 SDSEL3 SA9 104 VDDT SA11 105 SDSEL2 MEMR 106 VSST SA10 107 SDSEL1 LA18 108 SAR0 Am79C930 Pin No. Pin Name 109 SAR1 110 SAR2 111 SAR3 112 SAR4 113 SAR5 114 SAR6 115 TXC 116 VSST 117 ...
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... SAR4 70 SAR5 62 SAR6 38 SCE 11 SD0 79 SD1 83 SD2 82 SD3 133 SD4 58 SD5 90 SD6 124 SD7 123 SDCLK 122 SDDATA 46 SDSEL1 Am79C930 Pin No. Pin Name Pin No. 47 SDSEL2 105 71 SDSEL3 103 69 TCK 84 56 TDI 88 56 TDO 85 64 TEST 81 63 TMS 86 144 TRST 87 2 TXC ...
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... PCMCIA interface SRAM Chip Enable—this signal becomes asserted when the SRAM device 1 SCE has been addressed by either the 80188 core of the Am79C930 device or by the software through the PCMCIA interface eXtra Chip Enable—this signal becomes asserted when the extra peripheral 1 ...
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... Input with internal pulldown device Pin Function Type Output Type Size of Pullup Am79C930 Pin Style TS1 PTS1 TS1 PTS1 TS1 PTS1 TP1 TP1 TP1 TP1 PTS1 TS1 IPU PTS1 ...
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... INITDN bit of MIR9 set since this could lead to unaccept- able levels of power consumption by the Am79C930 de- vice. For more information on programmable pins, see the Multi-Function Pins section. Configuration Pins ...
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... IOWR is an active low signal. IOWR is asserted by the USER7/IRQ11 host system to indicate to the Am79C930 device that a write to the Am79C930’s I/O space is being performed. The Am79C930 device will not respond to the IOWR sig- nal until it has been configured for I/O operation by the system. Input ...
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... RESET is an active high-input signal that clears the Card Configuration Option Register CCOR) and places the Am79C930 device into an unconfigured (PCMCIA- Memory-Only Interface) state. This pin also causes a RESET to be asserted to each of the Am79C930 core function units (i.e., PCMCIA interface, CPU, and Trans- ceiver Attachment Interface). STSCHG Status Change The STSCHG signal is an active low signal ...
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... HIGH level, RESET causes the Am79C930 device to immediately place all ISA bus outputs into a high imped- ance state. This pin also causes a RESET to be as- serted to each of the Am79C930 core function units (i.e., ISA interface state machine, 80188, and Transceiver Attachment Interface). RFRSH ...
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... Input Some systems may require that the Am79C930 device deliver the transmit data according to a clock reference that is external to the Am79C930 device. In such sys- tems, the TXC pin may be configured as an input. TXDATA will change on falling edges of TXC, allowing ample setup and hold time for valid sampling of TXDATA with the rising edge of TXC ...
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... Preamble, SFD, PHY header, MAC header, Data and FCS field. The RXDATA input stream is expected to be NRZ data. Clock recovery is per- formed internal to the Am79C930 device external PLL is used for clock recovery, then the RXDATA input will expect valid data at rising edges of the RXCIN input ...
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... ADIN input of 3 higher. ADIN[1–2] A/D sample inputs ADIN[1–2] are inputs that accept single-ended analog input values for conversion by the internal Am79C930 A/D converter. Only one input will be sampled at any time for conversion by the internal Am79C930 device’s Output A/D circuit ...
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... TDI is the test data input path to the Am79C930 device. If left unconnected, this pin has a default value of HIGH. TDO Test Data Output TDO is the test data output path from the Am79C930 de- vice. TDO is tri-stated when the JTAG port is inactive. TMS Test Mode Select TMS is a serial input bit stream is used to define the spe- cific boundary scan test to be executed ...
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... In both 5 V and 3 V systems, these pins should be connected to a Ground ground supply. Multi-Function Pins The Am79C930 device includes a number of pins which have multiply-defined functions. The various functions assigned to each of these pins is determined through both device pin settings and through individual register Power bit settings ...
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... The USER0/RFRSH pin may be configured for input op- eration, output operation, or ISA RFRSH operation ac- cording to the following table: PCMCIA Pin USER4/ 0 LA17 Pin Data NA 1 (LA17 input function TIR29[4] Am79C930 STSCHG/ STSCHG/ BALE BALE TCR15[0] Pin Direction Pin Data (BALE input function ...
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... control the start of the TX state machine, provided that Am79C930 device firmware has enabled the operation by setting the TXS bit of TIR8. In addition to the functionality listed above, the USER1/IRQ12/EXTCTS/EXINT188 pin may be used to produce interrupts to the 80188 embedded controller. This capability is controlled by the U1INTCNT bits of ...
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... In addition to the functionality listed above, the USER6/IRQ5/EXTSDF pin may be used to enable the function of the RX state machine within the Am79C930 device. This capability is controlled by the ENXSDF bit and the ENXCHBSY bit, both of TCR28. When the ENXSDF bit and the ENXCHBSY bit of TCR28 are both ...
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... In addition to the functionality listed above, the USER5/IRQ4/EXTCHBSY pin may be used as the source for CCA information, instead of relying on the in- ternal CCA logic of the Am79C930 device. When using the external CCA information, CCA information from the internal logic will be unavailable. External CCA informa- ...
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... SDSEL[1] pin value without inversion, regardless of pin configuration setting. SDSEL[1] SDSEL[1] Pin Direction Pin Value HIGH O LOW Am79C930 reset default condition (when write to TIR2 occurs) (when write to TIR2 occurs) reset default condition reset default condition reset default condition reset default condition ...
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... While in this configuration, the internal TX state machine continues to operate with a reference clock derived from a divided version of the CLKIN input. Since the external TXC source is not driving the Am79C930 device TX state machine, there exists a TXCIN TCR30[ ...
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... TXPE Pin Direction Value O TXP_ON O TXP_ON TIR11[1] & TIR11[ Transmit state machine generated signals T1, T2, T3, TXP _ ON and O_TX have the timing indicated in the diagram in section Am79C930-Based TX Power Ramp Control. TXMOD Pin TXMOD Pin Direction Value TIR11[2] & ...
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... X O Transmit state machine generated signals T1, T2, T3, TXP _ ON and O_TX have the timing indicated in the diagram in section Am79C930-Based TX Power Ramp Control. Note that a read of the TXCMDT bit (TCR7[2]) will al- ways give the current TXCMD/LA21 pin value without inversion, regardless of pin configuration setting. ...
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... Memory Bus Interface Function The Am79C930 device contains a memory bus inter- face, which is used by the Am79C930 device to gain ac- cess to Flash memory for fetching 80188 instructions and to gain access to SRAM for fetching and storing driver commands, network data, and for temporary vari- able storage ...
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... PCMCIA slot in which the Am79C930-based design resides. The Common memory slave response function is always ac- tive on the Am79C930 device not possible to dis- able this function. The Am79C930 device does not attempt to interpret the ConfIndex value of the PCMCIA Configuration Option Register except for purposes of enabling the I/O slave response function ...
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... BSS register (SIR1) in order to allow system access to a total of 256K of Am79C930 memory re- sources. The total system I/O space required by the Am79C930 device is 16 bytes. The 40-byte I/O option is not available in the ISA Plug and Play mode of opera- tion. The EIOW bit (bit 2 of the BSS register (SIR1)) will be forced to 0 when the Am79C930 device has been placed into ISA Plug and Play mode ...
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... TAI. A separate internal chip select signal for the TAI exists to avoid confusion among slave devices. This sig- nal is not available on the Am79C930 memory interface bus, and therefore, memory interface cycles may be ob- served for which neither the Flash chip enable, nor the SRAM chip enable, nor the XCE signal is asserted ...
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... TAI section of the Am79C930 device.) The SCE signal may be attached to the CE in- put of an SRAM memory device external to the Am79C930 device 128K of SRAM may be ad- dressed by the 80188 core (with the exception that 64 bytes of SRAM space is mapped into internal Am79C930 registers of the BIU and TAI ...
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... The 80188 core accesses the Flash memory by assert- ing its Upper Chip Select (80188 UCS) This signal remains internal to the Am79C930 device. The internal UCS signal is routed into the BIU, since the 80188 core and the BIU must share the memory interface bus. The ...
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... In the ISA Plug and Play mode of operation, the number of programmable pins is reduced to 10, while the fixed function pins remain unchanged. The TAI is logically located on the Am79C930 memory interface bus as a slave-only device. The TAI contains 64 registers that are used to configure operational pa- rameters, to communicate commands, to pass data, and to pass status ...
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... Multi-Function Pin section of this document for more detail. The polarity of TXMOD and TXPE are programmable. A separate TXCMD signal (inverse polarity to TXCMD) is available. When RCEN Am79C930 AMD TGAP4 X TBCLK + 2 X TSCLK TGAP3 X TBCLK + 2 X TSCLK 2 X TSCLK 7 X TSCLK DRB X TBCLK ...
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... TXS bit of TIR8. These actions place the Am79C930 de- vice’s transmit state machine in a “wait for CTS” state. When the transceiver concludes that the medium is free ...
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... A/D device. The SAR pins are used as inputs in this mode to allow the externally converted value to be driven back into the Am79C930 device, so that it may be used in the CCA and Antenna Diversity logic circuits. In this mode, ADIN1 functions as the power control signal. ADIN1 be- ...
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... X reserved Because antenna switching can cause transient noise X reserved to appear at the RXD input of the Am79C930 device, the X D/A mode start of Baud Determination testing is delayed for a pe- riod of time immediately following the antenna switching process. In order to accommodate different transceiver/ antenna settling times, the amount of test start delay is programmable through the Baud Detect Start Timer of TCR16 ...
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... Am79C930 device’s internal CCA logic, which is de- scribed in the following paragraphs. The other possible CCA source is externally computed CCA information, which is then passed into the Am79C930 device through the USER5/IRQ4/EXTCHBSY pin. Regardless of the source of CCA information, a path through the Am79C930 TAI section is provided allowing the embed- ...
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... If the measured RSSI input value exceeds the programmed lower limit, then the result of this test is considered to be TRUE. The two tests mentioned above may be separately selected/deselected to serve as inputs to the Stop Am79C930 CCA Result (CHBSY Bit of TIR26) CHBSY = TRUE yes ...
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... For typical transceiver connections, the signal TXC is defined as an input to the transceiver. However, for some transceiver connections, the signal TXC is de- fined as a transceiver output . The Am79C930 device can accommodate both types of transceivers by allow- ing the TXC pin to be defined as either output or input. ...
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... This is an internal scan path for AMD internal testing use. Power Saving Modes Power Down Function The Am79C930 BIU includes five registers that are used to invoke a power-down function that will support the IEEE 802.11 (draft) specified power down by allowing variable lengths of power-down and power-up time. The ...
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... CIS READ operation will cause power down exit, but will proceed normally the Am79C930 device is operating in the ISA Plug and Play mode, then SIR0, SIR1, SIR2, and SIR3 registers will be the only locations that are still accessible when the Am79C930 device is in the power down mode ...
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... Power Down Length Count register values for each power down cycle. Software Access The Am79C930 device is directly driven by two pieces of software: (1) the device driver, which runs on the host machine’s CPU, performs transfers of data between the ...
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... OR OR 0000h – 000Fh 16 bytes performed with the Am79C930 device’s CE1 signal ac- tive. This means that there is aliasing of addresses in I/O space. This decode function is unaffected by the setting of the SIR1[2:0] register bits. PCMCIA Common Memory Resources — While the common memory space of the Am79C930 device only ...
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... AMD Some of the Am79C930 device’s PCMCIA Common Memory locations have predefined uses and, therefore, are not freely available to the device driver. Am79C930 Device PCMCIA Mode Common Memory Restricted Space PCMCIA Address in Common Memory SIR1[5:3] 0000h – 03FFh 0400h – 041Fh 0420h – ...
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... PCMCIA CIS information, since these bytes map to the upper 16 bytes of the Flash memory, which will be used by the 80188 core of the Am79C930 as the initial instruc- tion locations after reset. Note that the Configuration Tuple must contain the ...
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... PCMCIA I/O Resources — The Am79C930 device oc- cupies either bytes of I/O space, depending upon the setting of the EIOW bit (bit 2 of the BSS register (SIR1)). The I/O space of the Am79C930 contains the General Configuration Register, the Bank Switching Se- lect Register, and the set of 32 TIR registers. Addition- ally, all Am79C930 resources are accessible through I/O accesses, i ...
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... Flash memory for reading the Am79C930 device’s Plug and Play Resource Data. The following table indicates the range of I/O and mem- ory addresses to which the Am79C930 device will re- spond when operating in the ISA Plug and Play mode. Am79C930 ...
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... AMD Am79C930 Device ISA Plug And Play Mode Memory And I/O Resource Requirements Memory Range Memory Size MBA*+0000h – 32 Kbytes MBA*+7FFFh OR 0 bytes *MBA = ISA Plug and Play Memory Base Address **IOBA = ISA Plug and Play I/O Base Address Note that since the Am79C930 device’s memory ...
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... These conditions must be satisfied, since the Am79C930 device’s Bus Interface Unit will only use the upper 9 bits of the ISA memory address to determine when an address match has been achieved. Am79C930 Device ISA Plug And Play Mode Memory Restricted Space ISA Address in Memory SIR1[5:3] MBA+0000h – ...
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... ISA Plug and Play mode of operation. The EIOW bit (bit 2 of the BSS register (SIR1)) will be forced to 0 when the Am79C930 device has been placed into ISA Plug and Play mode. The I/O space of the Am79C930 device contains the General Configuration Register, the Bank Switching Select Reg- ister, and the set of 32 TIR registers ...
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... Am79C930 Device ISA Plug And Play Mode I/O MAP Resource Name Mnemonic SIR0: General SIR0: GCR Configuration Register SIR1: Bank Switching SIR1: BSS Select Register SIR2: Local Memory SIR2: LMAL Address [7:0] SIR3: Local Memory SIR3: LMAU Address [14:8] SIR4: I/O Data Port [7:0] SIR4: DPLL ...
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... AMD ISA Plug and Play Register Set — The Am79C930 de- vice fully supports the ISA Plug and Play specification, revision 1.0a. The Am79C930 device supports the Plug and Play Auto-configuration scheme. The Plug and Play Am79C930 Device ISA Plug And Play Mode Supported Auto-Configuration Ports ...
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... Am79C930 Device ISA Plug And Play Mode Plug And Play Register Set ISA Plug and Play Register Name Set READ_DATA port Serial Isolation Configuration Control Wake [CSN] Resource Data Status Card Select Number (CSN) Logical Device Number Unused Activate I/O Range Check ...
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... The Am79C930 device maps the Resource Data regis- ter accesses into 1K–16 of the upper 1 Kbytes of the Flash memory space so that Resource Data may be read from the Flash memory. Byte 0 of the Am79C930 device’s Resource Data is mapped to location 1 FC00h of the Flash memory. A maximum of 1K–16 bytes of Re- source Data is allowed by the Am79C930 design ...
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... SRAM Memory 0 0480h–1 FFFFh 1K–128 bytes FCE 96 Kbytes Flash Memory 0 8000h–1 FFFFh none 768 Kbytes FCE 96 Kbytes Flash Memory 0 0000h–1 FFFFh Am79C930 AMD Physical Location of Memory TIR 0–31 MIR 0–15 XCE locations 0–15 Undefined Physical Location of Memory TIR 0–31 MIR 0–15 XCE locations 0– ...
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... F FC00h–F FFEFh F FFF0h–F FFFFh MAC (80188 core) Interrupt Channel Allocation — The TAI and BIU sections of the Am79C930 device both generate interrupts to the 80188 core. TAI generated in- terrupts will always appear on the INT0 input of the 80188 core. BIU generated interrupts will always appear on the INT1 input of the 80188 core ...
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... Loopback Operation The Am79C930 device contains a loopback mode that is invoked by writing the LOOPB bit of TCR3[7]. When LOOPB is set then the Am79C930 device will perform an internal loopback of all transmissions. The data path transmitted will move out of the TX FIFO and be serialized. ...
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... CORESET (SIR0[6]) The CORESET bit of SIR0[6] can be used to reset the embedded controller and TAI sections of the Am79C930 device, along with a few locations in the MIR register space. When the CORESET bit is asserted, then the 80188 section of the Am79C930 device will be placed into reset, with behavior identical to that of a ...
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... Am79C930 device. Writing the value “111b” to bits two through zero of this register (i.e., bits [2:0]) will cause an internal RESET pulse to occur within the Am79C930 device). The RESET pulse will last for 14 CLKIN periods. This RESET will have the same effect as asserting the ...
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... The TIR space contains 32 registers which are used by the 80188 core to control the Am79C930 device’s TAI unit, to collect TAI status, and to transfer data to and from the TAI. These registers are accessible from both the system interface and the 80188 core ...
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... Disable Power Down Mode. When DISPWDN is set the Am79C930 device will be prevented from entering the power down mode. If the Am79C930 device is already in the power down mode when DISPWDN notes a transition from then the power down mode will be exited within three CLKIN periods. ...
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... EIOW is always 0 when the Am79C930 device has been set to the ISA Plug and Play mode of operation. EIOW is not writeable when the Am79C930 device has been set to the ISA Plug and Play mode of operation. 00 TAI Bank Select. When the EIOW bit is set to 0, then the TBS bits will act as Am79C930 memory interface bus address bits MA[4:3] during system interface accesses to the TIR registers ...
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... I/O space. Different I/O Data Ports do not imply a built in offset of LMA values. Description – These eight bits act as Am79C930 memory interface bus data bits MD[7:0] during system interface accesses to Flash and SRAM whenever any section of the I/O Data port is read or written. Am79C930 AMD ...
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... BIU is in direct memory access mode, such that system interface access cycles will have direct access to the Am79C930 memory interface. This mode should only be in- voked if the 80188 will be placed into HALT mode by an appropriate instruction within the 80188 firmware during the time that SIDA is set to 1 ...
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... Description 00h Lower 8 bits of the length of the power down cycle counter. The resolution of the power down length counter is in increments of PMX1/2 periods. The nominal PMX1/2 crystal Value is 32.768 kHz, resulting in a resolution of 31.25 s. Am79C930 AMD 81 ...
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... PMX1/2 has a frequency of 32.768 kHz. Description 00h Middle byte of the free running count. count is reset only when the reset pin is asserted. Timer resolution is 31.25 s when PMX1/2 has a frequency of 32.768 kHz. Description 00h Most significant byte of the free running count. Am79C930 ...
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... CLKIN input that is greater than 20 MHz in frequency. This information is needed in order to insure that the TAI section of the Am79C930 device is not pushed beyond design limits. Specifically, when CLKGT20 is set to 1, then the CLKIN signal is divided by 2 before being fed to the TAI section. ...
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... WAKEUP bit of the PCMCIA CCSR is set then this bit may be written with a 1 and writing this bit has no effect. If the STSCHGFN bit of TCR15 has been set then STSCHGD is reset automatically whenever the WAKEUP bit of the Am79C930 Number Of Wait States Used By Arbitration Logic For ...
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... PCMCIA CCSR is RESET the STSCHGFN bit of TCR15 has been set then the value that is written to this bit will be inverted and driven to the STSTCHG pin of the Am79C930 device. The value that is read from this bit always represents the inverse of the current value of the STSTCHG pin of the Am79C930 device ...
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... BSS register (SIR1)). The following tables give the address for each of the directly accessi- ble TIRs for each of the system interface modes for each of the two mapping schemes, as well as the address for each register as it appears in the memory map of the 80188 embedded core. Am79C930 ...
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... Am79C930 AMD ISA Plug 80188 Core and Play Address in I/O Address Memory IOBA+0008h mem 400h IOBA+0009h mem 401h IOBA+000Ah mem 402h IOBA+000Bh mem 403h IOBA+000Ch mem 404h IOBA+000Dh mem 405h IOBA+000Eh ...
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... Am79C930 80188 Core PCMCIA Address in I/O Address Memory 0008h mem 400h 0009h mem 401h 000Ah mem 402h 000Bh mem 403h 000Ch mem 404h 000Dh mem 405h 000Eh mem 406h 000Fh mem 407h ...
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... Multi-Function Pin section. 0 TAI reset. Active high. Asserting this bit will reset the TAI portion of the Am79C930 device, except for this register (i.e., TIR0). 0 Software Strobe. This bit is intended for software development use. The value written to this bit will be sent to the test output when the device is programmed for test mode. – ...
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... Multi-Function Pin section. 0 Serial Device Data Tristate. When SDDT is set to 1, the SDDATA pin of the Am79C930 device is tri-stated. When SDDT is set to 0, the SDDATA pin is driven with the value of the SDD bit. The complete control of the function of the SDDATA pin is de- scribed in the Multi-Function Pin section ...
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... Antenna Switch. This bit will become set at the end of each time slot as programmed in the Antenna Diversity Timer Register (TCR4) to indicate that the channel tests for this antenna selection have been completed. This bit is reset to 0 when the RXRES bit of TIR16 is set written to ANTSW. Am79C930 AMD ...
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... TXDONE will be set when the last data bit for the frame has been sent. 0 CRC Start. CRCS will be set the Am79C930 device when the first bit of the CRC is being transmitted. If the NO TX CRC option has been set, then CRCS will not become set. ...
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... ALOKI indicates the cessation of antenna diversity activity so that the incoming network signal can be tracked and decoded by the DPLL. ALOKI will be set the Am79C930 device when the conditions for stopping the antenna diversity switching as set up in the Baud Detect Circuit Control Registers, TCR17, TCR18, TCR20, ...
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... The transmit busy bit will be set in the transmit status register (TIR9) to indicate the state of transmit. Resetting this bit to 0 during transmission will not cause the current transmission to be aborted. Transmission abort is performed with the TXRES bit. Am79C930 th byte that follows the last bit of the Start of Transmitted CRC ...
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... A TXFC value of “0h” indicates a full TX FIFO, i.e., 0 spaces are available Busy. This bit is set the Am79C930 device when the transmit operation begins and remains set until the transmission has completed. Specifically, the TXBSY bit will be active whenever the internal O_TX signal is active as indicated in the TX timing dia- gram found in the Am79C930-based TX Power Ramp Control section ...
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... LLOCKE/SA15 pin, depending upon the values of the LLOCKEN bit (TCR14[6]), and the operating mode of the Am79C930 device (i.e., PCMCIA or ISA). The value read from LLOCKE will always represent the current value of the LLOCKE/SA15 pin. The control of the function of the LLOCKE/SA15 pin is described in the Multi-Function Pin section ...
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... TX frame. During RX, when the byte count limit is reached, an interrupt to the 80188 controller will be generated if the RXBCNT interrupt has been unmasked. During RX, the byte counter counts all bytes that follow the Start of Frame Delimiter. Byte count limit FIFO operations. Am79C930 AMD has no effect on state machine ...
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... CRC was good. 0 CRC8 Good. The CRC8 machine has detected a good CRC and has latched the byte count that was active at the time that the CRC was good. Am79C930 ...
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... RXFC value of “Fh” indicates a full RX FIFO Busy. This bit is set the Am79C930 device when the RXS bit of TIR16 is set to a one, and remains set until the RXRES bit of TIR16 is set to a one, or until any other global reset is activated (e ...
Page 100
... MAC firmware. Note that all bytes beginning with the first byte following the Start of Frame Delimiter and including the CRC bytes are included in the CRC8 Correct Count value, but the bytes that are included in the CRC8 calculation are dependent upon the setting of the PFL bits of TCR3. Am79C930 ...
Page 101
... Channel Busy. The Am79C930 device will set this bit when the clear channel assessment logic determines that a carrier is pre- sent. The Am79C930 device will set this bit when the clear channel assessment logic determines that a carrier is not present. Writes by firmware will have no effect on this bit. ...
Page 102
... SAR in the A/D circuit. Description 0 Conversion Active. When an A/D conversion is being performed, the Am79C930 device will set this bit When the conversion operation has completed, the Am79C930 device will reset this bit pin Serial Approximation Register. Contains the A/D converter’s Serial Approximation Register value ...
Page 103
... RSSI Equal or Above Limit. When the converted RSSI input value equals or exceeds the value in the RSSI lower limit register, then the Am79C930 device will set this bit When the converted RSSI input value is less than the value in the RSSI lower limit regis- ter, then the Am79C930 device will set this bit ...
Page 104
... CLKIN = 20MHz and CLKGT20 = 0, the resolution Start Delimiter. The value in this register determines the number of bytes of preamble that will be verified before the start of frame detect indication is asserted during frame reception and transmission. The following interpretations have been assigned to these bits. Am79C930 ...
Page 105
... Transmit Data Pin Control. These bits are used to control the state of the TXDL pin when no transmit activity is present. The following interpretations have been assigned to these bits: TXDC[1: Am79C930 AMD Programmed Register None TCR10 TCR9, TCR10 TCR8, TCR9 TCR10 ...
Page 106
... Physical layer Field Length [3:0]. These bits are used to determine the number of bytes of PHY header that are allowed to pass before the Am79C930 device begins calculating the CRC8 and CRC32 and DC bias control. The Physical layer Field Length value is used Am79C930 ...
Page 107
... CLKIN period when the CLKGT20 bit of MIR9 is set to 0 and a resolution equal to 40 times the CLKIN period when the CLKGT20 bit of MIR9 is set to 1. For a 1 Mbs data rate with CLKIN = 20 MHz and CLKGT20 = 0, the resolution Am79C930 AMD 107 ...
Page 108
... The control of the function of the USER6/IRQ5 pin is described in the Multi-Function Pin section. 0 USER5 Function. USER5FN, the PCMCIA mode pin, USER5EN (TCR15[2]), and ISA PnP registers 70h and 71h are used to deter- mine the function of the USER5/IRQ4 pin. Am79C930 ...
Page 109
... ISA Plug and Play configuration software. When this procedure is followed, then the system designer can be assured that the IRQ12 function will not be used by the Am79C930 device, and therefore, the USER1/IRQ12 pin will remain in the high-imped- ance state and will be available for connection to an interrupt gener- ating source in the design ...
Page 110
... Configuration Register (TCR0). Start of Frame detection is performed on the bits in the order that they appear on the medium, with the SDLT LSB, bit 0, being checked against the first bit to arrive at the Am79C930 (RX case) or the first bit to leave the Am79C930 (TX case) and continuing in that order. 0Ah ...
Page 111
... SD[1:0] bits in the Network Configuration Register (TCR0). Start of Frame detection is performed on the bits in the or- der that they appear on the medium, with the SDLT LSB, bit 0, being checked against the first bit to arrive at the Am79C930 (RX case) or the first bit to leave the Am79C930 (Tx case) and continuing in that order. ...
Page 112
... PCMCIA pin is set to 1, then the LLOCKE/SA15 pin is enabled to drive both high and low output values. LLOCKE output values are determined by the LLOCKE bit of TIR11. When LLOCKEN is reset then the LLOCKE pin is forced to a high- impedance state. Reads of the LLOCKE bit of TIR11 will yield the Am79C930 ...
Page 113
... USER6 Enable. USER6EN, the USER6FN bit of TCR15, the ISA PnP interrupt level select register, the ISA PnP interrupt type regis- ter, and the PCMCIA pin are used to determine the function of the USER6IRQ5 pin. The control of the function of the USER6/IRQ5 pin is described in the Multi-Function Pin section. Am79C930 AMD 113 ...
Page 114
... CLKIN period when the CLKGT20 bit of MIR9 is set to 0 and a resolution equal to 40 times the CLKIN period when the CLKGT20 bit of MIR9 is set to 1. For a 1 Mbs data rate with CLKIN = 20 MHz and CLKGT20 = 0, the resolution Am79C930 ...
Page 115
... CLKIN periods (with CLKGT20=0 each baud tick is one CLKIN period, with CLKGT20=1, each baud tick is two CLKIN periods) will all yield a rising edge baud counter value of 20. The same is true for the falling Am79C930 AMD 115 ...
Page 116
... The value in this register is treated as a radix 2 positive real number with two decimal places. The lowest practi- cal value possible is 0.25 (=00.01) and the highest prac- tical value is 3.75 (=11.11). Am79C930 ...
Page 117
... Fail[5:0] The value of these bits indicates the current number of bad transitions detected by the baud detector. This is a read-only register. measure of the time of RSSI sample relative to the an- tenna switching event. A register value of 0 means that no RSSI samples will be taken. Am79C930 AMD 117 ...
Page 118
... A/D converter in CCA and antenna diversity decisions. ENEXT is used in conjunction with ENSAR (TCR25[5]) and ADDA (TIR26[2]) to configure the Am79C930 device A/D mode according to the table listed in section RSSI A/D Unit . 0 Enable SAR. Setting ENSAR enables the SAR[6:0] pins to drive as outputs ...
Page 119
... CLKIN periods if CLKGT20=1). This fact is important when using an external A/D converter in the external A/D mode. Minimum value in the A2DT[3:0] field must be 0001. A value of 0000 is not allowed. ADT[5:0]=TCR4[5: when CLKGT20 = 0 Am79C930 AMD SS[5:0]=TCR24[5:0] A2DT[3:0]=TCR25[3:0]+ 20138B-9 119 ...
Page 120
... TXMOD Polarity. When this bit is set then the polarity of the 0 TXMOD output will be low assert, such that when the TGAP2 counter expires, the TXMOD pin will be driven to a LOW logic level. When this bit is set then the polarity of the TXMOD output will Am79C930 ...
Page 121
... CHBSYC interrupt of TIR4 (bit 7) and the BCF interrupt bit of TIR5. When ENXCHBSY is set then antenna diversity switching is disabled and the receive function of the Am79C930 device must be enabled by a positive indication of SDF on the USER6/IRQ5 input pin. When ENXCHBSY is set to 0, then the source for CCA indication is the internal CCA determination logic ...
Page 122
... X version of the CLKIN input, where X is deter- mined by the setting of the DR bits of TCR30. When set the TXC pin functions as an input, allowing the data rate of the transmit operations to be set by an external source. When TXCIN is set to 1, Am79C930 ...
Page 123
... FIFO is inserted into the TX data path. This FIFO allows for some mismatch to be tolerated in the clock rates between the Am79C930 internal transmit clock and the external TXC clock that is connected to the TXC input. Because of this inter- nal FIFO, the appearance of transmit data from the setting of the TXS bit in TIR8 will be delayed by 8 bit times whenever the TXCIN bit has the value of 1 ...
Page 124
... Read only This bit is written by the host to indicate that the host is only capable of 8-bit I/O accesses. This bit is ignored by the Am79C930 device, since the Am79C930 device is only capable of 8-bit I/O accesses. 0 WAKEUP is used with the STSCHGFN bit of TCR15 to determine the function of the STSCHG pin. When the STSCHGFN bit of ...
Page 125
... When written with a 1, the PWRDWN bit generates an interrupt to the 80188, requesting that the 80188 core place the Am79C930 de- vice into the power down state. The interrupt is signaled in MIR0, bit 5. If written with a 0 while in power down mode, power down mode is exited ...
Page 126
... Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. DC CHARACTERISTICS 5.0 V Am79C930 DC Characteristics Parameter Symbol Parameter Description VIL Input LOW Voltage ...
Page 127
... DC CHARACTERISTICS (continued) 5.0 V Am79C930 DC Characteristics Parameter Symbol Parameter Description IDDPD2 Power Supply Current IDDPD3 Power Supply Current CIN Input Pin Capacitance CO I/O or Output Pin Capacitance CCLK BCLK Pin Capacitance Notes OL1 = 4mA applies to the following pins: STSCHG , PWRDWN, MA[16:0], MD[7:0], FCE, SCE, XCE, MOE, MWE, TDO, LFPE , LFCLK, LLOCKE, HFPE, INPACK, HFCLK, ANTSLT, ANTSLT, TXCMD, TXCMD, TXPE, TXDATA, TXDATA, TXMOD, RXPE, FDET, SDCLK, SDDATA, SDSEL [3:1], SAR[6:0], USER[4:2], USER[0], TXC, ADIN1, ADIN2 ...
Page 128
... Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. 3.3 V Am79C930 DC CHARACTERISTICS Parameter Symbol Parameter Description VIL Input LOW Voltage ...
Page 129
... DC CHARACTERISTICS (continued) 3.3 V Am79C930 DC Characteristics Parameter Symbol Parameter Description IDDPD2 Power Supply Current IDDPD3 Power Supply Current CIN Input Pin Capacitance CO I/O or Output Pin Capacitance CCLK BCLK Pin Capacitance Notes OL1 = 2.4mA applies to the following pins: STSCHG , PWRDWN, MA[16:0], MD[7:0], FCE, SCE, XCE, MOE, MWE, TDO, LFPE , LFCLK, LLOCKE, HFPE, INPACK, HFCLK, ANTSLT, ANTSLT, TXCMD, TXCMD, TXPE, TXDATA, TXDATA, TXMOD, RXPE, FDET, SDCLK, SDDATA, SDSEL [3:1], SAR[6:0], USER[4:2], USER[0], TXC, ADIN1, ADIN2 ...
Page 130
... V DD DD5 Operating ranges define those limits between which the func- tionality of the device is guaranteed. Test Conditions IOL = 2.0 mA IOH = –0.4 mA VDD = 5 0.5 V VDD = 5 2.7 V VDD = 5 0.5 V VDD = 5 2.7 V VOUT = 0.4 V VOUT = VDD Am79C930 ) . . . . . . . . . . . . . . . . . DDT DDU1 DDU2 DDM + ...
Page 131
... Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins instruction fetch cycle to FLASH memory. 2 PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188 controller access. 3 Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle. ...
Page 132
... Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins instruction fetch cycle to FLASH memory. 2 PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188 controller access. 3 Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle. ...
Page 133
... Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins instruction fetch cycle to FLASH memory. 2 PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188 controller access. 3 Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle. ...
Page 134
... Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins instruction fetch cycle to FLASH memory. 2 PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188 controller access. 3 Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle. ...
Page 135
... All inputs within the range – where V DD for a given input pin. (See section on power supply pin descriptions unless otherwise noted Operating ranges define those limits between which the func- tionality of the device is guaranteed. Am79C930 AMD ) . . . . . . . . . . . . . . . . . ...
Page 136
... Host performs ISA WRITE cycle at same time that Am79C930 embedded 80188 controller begins instruction fetch cycle to FLASH memory. 2 ISA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188 controller access. 3 Host performs ISA READ cycle immediately following completion of ISA WRITE cycle. ...
Page 137
... Notes 1, 2 Note 1 Note 2 Note 2 Am79C930 AMD ) . . . . . . . . . . . . . . . . . DDT DDU1 DDU2 DDM 4. 5. ...
Page 138
... TCLKIN-10 Note 1 TCLKIN-10 Note wait states 1 wait state 2 wait states Note 2 TCLKIN-15 Note TCLKIN-10 Am79C930 Min Max Unit ...
Page 139
... Notes 1, 2 Note 1 Note 2 Note 2 Am79C930 AMD ) . . . . . . . . . . . . . . . . . DDT DDU1 DDU2 DDM 3 ...
Page 140
... TCLKIN-10 Note 1 TCLKIN-10 Note wait states 1 wait state 2 wait states Note 2 TCLKIN-15 Note TCLKIN-10 Am79C930 Min Max Unit 2 100 ns 2 100 ns 2 100 100 ns ns ...
Page 141
... All inputs within the range – where V DD for a given input pin. (See section on power supply pin descriptions unless otherwise noted Operating ranges define those limits between which the func- tionality of the device is guaranteed. Am79C930 AMD ) . . . . . . . . . . . . . . . . . ...
Page 142
... Note 8 Notes Notes Notes Notes 1, 8 Notes 1, 8 Notes 2, 7 Notes 2, 7 Notes 2, 7 Notes 2, 8 Notes 2, 8 Note 6 Note 6 Notes 1, 3 Notes 2, 4 Notes 2, 4 Notes 2, 3 Am79C930 Min Max Unit ...
Page 143
... T TXLHO is 15 ns, regardless of DR value. 8. Parameter not included in the production test RXDS min = 110–CLKP X T CLKIN t RXDH min = 10+CLKP X T CLKIN t RXDS min = 110–CLKP X T CLKIN RXDH min = 10+CLKP X T CLKIN X 2 Am79C930 AMD 143 ...
Page 144
... All inputs within the range – where V DD for a given input pin. (See section on power supply pin descriptions unless otherwise noted Operating ranges define those limits between which the func- tionality of the device is guaranteed. Am79C930 ) . . . . . . . . . . . . . . . . . ...
Page 145
... Note 6 Note 6 Notes 1, 3 Notes 2, 4 Notes 2, 4 Notes RXDS min = 110–CLKP X T CLKIN t RXDH min = 10+CLKP X T CLKIN t RXDS min = 110–CLKP X T CLKIN RXDH min = 10+CLKP X T CLKIN X 2 Am79C930 AMD Min Max Unit ...
Page 146
... V DD for a given input pin. (See section on power supply pin descriptions unless otherwise noted Operating ranges define those limits between which the func- tionality of the device is guaranteed. Test Conditions Note 1 Note 1 Am79C930 ) . . . . . . . . . . . . . . . . . ...
Page 147
... unless otherwise noted Operating ranges define those limits between which the func- tionality of the device is guaranteed. Test Conditions Note 1 7 bits 4 bits 1.25 to 1.75 V (ADREF x 2) Am79C930 AMD ) . . . . . . . . . . . . . . . . . ...
Page 148
... Figure 5. PCMCIA MEMORY WRITE Access Timing Diagram 148 AVQV t ELQV t ELGL t GLQV t AVGL t GLWTV t WTLWTH t GLQNZ t AVWH t ELWH t ELWL t WLWH t AVWL t WLWTV t WTLWTH t GHWL t DVWH t WLQZ t GHQZ Am79C930 t GHAX t GHEH t GHQZ t QVWTH 20138B-10 t WMAX t GHEH t WHGL t WTHWH t WMDX t WHQNZ t GLQNZ 20138B-11 ...
Page 149
... AVIWL REG t RGLIWL CE t ELIWL IOWR tI WLWTL WAIT t DVIWL D i (Din) Figure 7. PCMCIA I/O WRITE Access Timing Diagram t IGLIGH t WTHQV t WTLWTH t IGLQV t IGQNZ tI WHAX t IWHRGH tI WHEH t IWLIWH tWTHIWH t WTLWTH t IWHDX Am79C930 AMD t IGHAX t IGHRGH t IGHEH t IGHIAH t IGHQX t IGHQZ 20138B-12 20138B-13 149 ...
Page 150
... Figure 8. ISA All Access Timing Diagram Am79C930 20138B-14 ...
Page 151
... RDSC t m OLZ data sampled at this point valid Am79C930 AMD RDHC valid 20138B- ...
Page 152
... AMD CLOCK WAVEFORMS CLKIN TXC RXC 152 CLIN 2 CHIN 0 INLH t INHL t CLKIN t CLTX 2 CHTX 0 TXLH t TXHL t TXC t CLRX 2 CHRX 0 RXLH t RXHL t RXC Figure 11. CLOCK Timing Diagram Am79C930 0.8 V 0.8 V 0.8 V 20138B-17 ...
Page 153
... Internally Controlled Output RXC RXD TXC (input) TXD TXC (output) TXD Figure 12. TAI Timing Diagram t RXDS t RXDS t TXDD t TXDV t TXDS t TXDH Figure 13. Serial Data Timing Diagram Am79C930 AMD 20138B-18 20138B-19 153 ...
Page 154
... AMD PROGRAMMABLE INTERFACE WAVEFORMS CLKIN CLKOUT (internal) WAIT or IOCHRDY RCO** (data change) RCO** (drive change) RCO** (drive change) **RCO = Register Controlled Output Figure 14. Programmable Interface Timing Diagram 154 Am79C930 20138B-20 ...
Page 155
... IEEE 1149.1 INTERFACE WAVEFORMS TCK TDI, TMS TDO Output Signals Input Signals Figure 15. IEEE 1149.1 Timing Diagram Am79C930 AMD t 35 20138B-21 155 ...
Page 156
... Figure 17. 3.3 V PCMCIA AC Test Reference Waveform 156 the PCMCIA power supply pins are set to 5.0 V (i.e., VDDP pins = 5.0 V). 2.4 0.8 2.4 0.8 measured parameter value the PCMCIA power supply pins are set to 3.3 V (i.e., VDDP pins = 3.3 V). 2.0 0.8 2.0 0.8 measured parameter value Am79C930 20138B-22 20138B-23 ...
Page 157
... Bus Interface signals, IEEE 1149.1 signals and any other signal not considered to be part of the PCMCIA bus interface. 2.0 0.8 2.0 0.8 measured parameter value Interface signals, IEEE 1149.1 signals and any other signal not considered to be part of the PCMCIA bus interface. 2.0 0.8 2.0 0.8 measured parameter value Am79C930 AMD 20138B-24 20138B-25 157 ...
Page 158
... AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. PCnet is a trademark of AMD. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 158 19.80 20.20 21.80 22.20 11 – 13 1.60 MAX 11 – 13 0.50 BSC 0.17 0.27 Am79C930 21.80 22.20 19.80 20.20 16-038-PQT-2_AH PQT144 5-4-95 ae ...
Page 159
... The general function of the Am79C930 device is to pro- vide the MAC layer functions for an IEEE 802.11 (draft) or Xircom Netwave protocol network. The following sec- tions give a description of the interaction of the Am79C930 device with a device driver, the Am79C930 80188 core firmware, and the network ...
Page 160
... SRAM data buffer space and will examine the desti- nation address. If the address does not match the ad- dress of the Am79C930 subsystem, then the frame will be rejected by the Am79C930 device. If the frame ad- dress does match the address of the Am79C930 subsystem, then the frame will be accepted. When all bytes of the receive frame have been placed into the SRAM’ ...
Page 161
... Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am186, Am386, Am486, Am29000, b IMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet, PCnet- FAST , PCnet- FAST +, PCnet-Mobile, QFEX, QFEXr, QuASI , QuEST, QuIET, TAXIchip, TPEX, and TPEX Plus are trademarks of Advanced Micro Devices, Inc ...