89hpes16t4g2 Integrated Device Technology, 89hpes16t4g2 Datasheet

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89hpes16t4g2

Manufacturer Part Number
89hpes16t4g2
Description
16-lane, 4-port Gen2 Pcie I/o Expansion Switch
Manufacturer
Integrated Device Technology
Datasheet
Device Overview
Express® switching solutions. The PES16T4G2 is a 16-lane, 4-port
Gen2 peripheral chip that performs PCI Express Base switching with a
feature set optimized for high performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and up to
three downstream ports and supports switching between downstream
ports.
Features
Block Diagram
© 2008 Integrated Device Technology, Inc.
The 89HPES16T4G2 is a member of IDT’s PRECISE™ family of PCI
– Sixteen 5 Gbps Gen2 PCI Express lanes
– Four switch ports
– Low latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 2.0 compliant
High Performance PCI Express Switch
• One x4 upstream port
• Three x4 downstream ports
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
(Port 0)
SerDes
Logical
Layer
Phy
Frame Buffer
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
®
16-Lane 4-Port
Gen2 PCI Express® Switch
Multiplexer / Demultiplexer
Transaction Layer
4-Port Switch Core / 16 PCI Express Lanes
Data Link Layer
(Port 2)
SerDes
Logical
Layer
Phy
Route Table
Figure 1 Internal Block Diagram
1 of 32
Multiplexer / Demultiplexer
Arbitration
– Automatic per port link width negotiation to x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Ability to load device configuration from serial EEPROM
– PCI compatible INTx emulation
– Bus locking
– Incorporates on-chip internal memory for packet buffering and
– Integrates sixteen 5 Gbps embedded SerDes with 8b/10b
– Internal end-to-end parity protection on all TLPs ensures data
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
– Supports Hot-Swap
Transaction Layer
Flexible Architecture with Numerous Configuration Options
Legacy Support
Highly Integrated Solution
Reliability, Availability, and Serviceability (RAS) Features
Data Link Layer
Port
• Receive equalization (RxEQ)
queueing
encoder/decoder (no separate transceivers needed)
integrity even in systems that do not implement end-to-end
CRC (ECRC)
boards
(Port 4)
SerDes
Logical
Layer
Phy
Scheduler
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
89HPES16T4G2
(Port 6)
SerDes
Logical
Layer
Phy
Data Sheet
March 27, 2008
DSC 6928

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89hpes16t4g2 Summary of contents

Page 1

... Device Overview The 89HPES16T4G2 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions. The PES16T4G2 is a 16-lane, 4-port Gen2 peripheral chip that performs PCI Express Base switching with a feature set optimized for high performance applications such as servers, storage, and communications/networking ...

Page 2

... IDT 89HPES16T4G2 Data Sheet ◆ Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – Support PCI Express Power Management Interface specifica- tion (PCI-PM 2.0) – Unused SerDes are disabled. – Supports Advanced Configuration and Power Interface Spec- ification, Revision 2.0 (ACPI) supporting active link state ◆ ...

Page 3

... IDT 89HPES16T4G2 Data Sheet As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES16T4G2 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES16T4G2 registers supports SMBus arbitration ...

Page 4

... IDT 89HPES16T4G2 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES16T4G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level ...

Page 5

... IDT 89HPES16T4G2 Data Sheet Signal SSMBADDR[5,3:1] SSMBCLK SSMBDAT Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] Type Name/Description I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus ...

Page 6

... IDT 89HPES16T4G2 Data Sheet Signal GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] Signal CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT SWMODE[2:0] Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P6RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 6. ...

Page 7

... IDT 89HPES16T4G2 Data Sheet Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Signal REFRES0 REFRES2 REFRES4 REFRES6 V CORE PEA DD V PEHA DD V PETA Type Name/Description I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle ...

Page 8

... IDT 89HPES16T4G2 Data Sheet Pin Characteristics Note: Some input pads of the PES16T4G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption ...

Page 9

... IDT 89HPES16T4G2 Data Sheet Function EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N SerDes Reference REFRES0 Resistors REFRES2 REFRES4 REFRES6 1. Internal resistor values under typical operating conditions are 92K Ω for pull-up and 90K Ω for pull-down. 2. Schmitt Trigger Input (STI). Pin Name ...

Page 10

... IDT 89HPES16T4G2 Data Sheet Logic Diagram — PES16T4G2 Reference Clocks Reference Clock Frequency Selection PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 4 PCI Express Switch SerDes Input Port 6 Master SMBus Interface ...

Page 11

... IDT 89HPES16T4G2 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter Description Refclk Input reference clock frequency range FREQ T Rising edge rate C-RISE T Falling edge rate C-FALL V Differential input high voltage ...

Page 12

... IDT 89HPES16T4G2 Data Sheet Parameter T Maximum time to transition to a valid Idle after sending TX-IDLE-SET-TO- an Idle ordered set IDLE T Maximum time to transition from valid idle to diff data TX-IDLE-TO-DIFF- DATA T Transmitter data skew between any 2 lanes TX-SKEW T Minimum Instantaneous Lone Pulse Width ...

Page 13

... IDT 89HPES16T4G2 Data Sheet Signal JTAG JTAG_TCK 1 JTAG_TMS , JTAG_TDI JTAG_TDO JTAG_TRST_N 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state ...

Page 14

... IDT 89HPES16T4G2 Data Sheet Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PEA PCI Express Analog Power PEHA PCI Express Analog High Power DD V PETA PCI Express Transmitter Analog Voltage DD V Common ground SS 1 ...

Page 15

... IDT 89HPES16T4G2 Data Sheet Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below) ...

Page 16

... IDT 89HPES16T4G2 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Serial Link PCIe Transmit V Differential peak-to-peak output TX-DIFFp-p 2 voltage V Low-Drive Differential Peak to TX-DIFFp-p-LOW ...

Page 17

... IDT 89HPES16T4G2 Data Sheet I/O Type Parameter Description Serial Link PCIe Receive (cont.) V Differential input voltage (peak- RX-DIFFp-p to-peak) RL Receiver Differential Return RX-DIFF Loss RL Receiver Common Mode Return RX-CM Loss Z Differential input impedance RX-DIFF-DC (DC common mode impedance RX--DC Z Powered down input common RX-COMM-DC ...

Page 18

... IDT 89HPES16T4G2 Data Sheet I/O Type Parameter Description Capacitance C IN Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0. 2. Depending upon conditions, values may fall outside the range specified with the default settings. Register settings are available to optimize values as needed. ...

Page 19

... IDT 89HPES16T4G2 Data Sheet Package Pinout — 288-BGA Signal Pinout for PES16T4G2 The following table lists the pin numbers and signal names for the PES16T4G2 device. Pin Function Alt Pin A1 V B13 B14 I/O B15 CORE B16 DD A5 PE6RP03 ...

Page 20

... IDT 89HPES16T4G2 Data Sheet Pin Function Alt Pin L1 V R21 R22 PEHA L19 V PEA T3 DD L20 L21 REFRES4 T19 L22 V T20 T21 SS M2 REFRES2 T22 PEA U2 DD M19 M20 V PEHA ...

Page 21

... IDT 89HPES16T4G2 Data Sheet Alternate Signal Functions No Connection Pins Pin GPIO Alternate AA21 GPIO_00 P2RSTN AA22 GPIO_01 P4RSTN Y22 GPIO_02 IOEXPINTN0 H21 GPIO_04 IOEXPINTN2 E20 GPIO_07 GPEN D21 GPIO_11 P6RSTN Table 19 PES16T4G2 Alternate Signal Functions NC Pins B10 K21 N2 AA13 AA19 AA20 ...

Page 22

... IDT 89HPES16T4G2 Data Sheet Power Pins V Core A10 A13 A16 D18 D22 K22 N1 N22 T1 T22 V19 W5 AB4 AB7 AB10 AB13 AB16 V I/O V PEA V PEHA A19 D8 B13 C8 D11 B16 C22 D13 C12 D2 D16 C17 H20 E19 F3 R2 ...

Page 23

... IDT 89HPES16T4G2 Data Sheet Ground Pins D17 M21 A2 E2 M22 A11 F2 N20 A12 F4 P4 A22 F19 P19 B12 G22 P20 B14 H2 P21 B15 J2 R21 B17 J3 U4 B18 J4 U19 B19 J19 U21 B22 K3 V2 C11 L1 V3 C13 L2 V21 C14 ...

Page 24

... IDT 89HPES16T4G2 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE No Connection PE0RN00 ...

Page 25

... IDT 89HPES16T4G2 Data Sheet Signal Name PE0RN03 PE0RP00 PE0RP01 PE0RP02 PE0RP03 PE0TN00 PE0TN01 PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE2RN00 PE2RN01 PE2RN02 PE2RN03 PE2RP00 PE2RP01 PE2RP02 PE2RP03 PE2TN00 PE2TN01 PE2TN02 PE2TN03 PE2TP00 PE2TP01 PE2TP02 PE2TP03 PE4RN00 PE4RN01 PE4RN02 PE4RN03 PE4RP00 PE4RP01 ...

Page 26

... IDT 89HPES16T4G2 Data Sheet Signal Name PE4RP03 PE4TN00 PE4TN01 PE4TN02 PE4TN03 PE4TP00 PE4TP01 PE4TP02 PE4TP03 PE6RN00 PE6RN01 PE6RN02 PE6RN03 PE6RP00 PE6RP01 PE6RP02 PE6RP03 PE6TN00 PE6TN01 PE6TN02 PE6TN03 PE6TP00 PE6TP01 PE6TP02 PE6TP03 PEREFCLKN0 PEREFCLKP0 PERSTN REFCLKM REFRES0 REFRES2 REFRES4 REFRES6 RSTHALT I/O Type ...

Page 27

... IDT 89HPES16T4G2 Data Sheet Signal Name SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 V CORE PEA, V PEHA PETA I/O Type Location I AA17 I Y18 I AA18 I/O, See Table 21 for a listing of power pins. See Table 22 for a listing of ground pins. ...

Page 28

... IDT 89HPES16T4G2 Data Sheet PES16T4G2 Pinout — Top View Core (Power I/O (Power) DD Vss (Ground ...

Page 29

... IDT 89HPES16T4G2 Data Sheet PES16T4G2 Package Drawing — 288-Pin BX288/BXG288 March 27, 2008 ...

Page 30

... IDT 89HPES16T4G2 Data Sheet PES16T4G2 Package Drawing — Page Two March 27, 2008 ...

Page 31

... IDT 89HPES16T4G2 Data Sheet Revision History March 27, 2008: Initial publication of final data sheet March 27, 2008 ...

Page 32

... IDT 89HPES16T4G2 Data Sheet Ordering Information NN A AAA NNAN Product Operating Device Product Family Family Voltage Detail Valid Combinations 89HPES16T4G2ZABX 288-ball SBGA package, Commercial Temperature 89HPES16T4G2ZABXG 288-ball Green SBGA package, Commercial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 ® ...

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