89hpes10t4bg2 Integrated Device Technology, 89hpes10t4bg2 Datasheet
89hpes10t4bg2
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89hpes10t4bg2 Summary of contents
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... Device Overview The 89HPES10T4BG2 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions. The PES10T4BG2 is a 10-lane, 4- port Gen2 peripheral chip that performs PCI Express Base switching with a feature set optimized for high performance applications such as servers, storage, and communications/networking. It provides connec- ...
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... IDT 89HPES10T4BG2 Data Sheet ◆ Reliability, Availability, and Serviceability (RAS) Features – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC and Advanced Error Reporting – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – ...
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... IDT 89HPES10T4BG2 Data Sheet As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES10T4BG2 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES10T4BG2 registers supports SMBus arbitration ...
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... IDT 89HPES10T4BG2 Data Sheet Signal PE0RN[3:0] PE0RP[3:0] PE0TN[3:0] PE0TP[3:0] PE2RN[1:0] PE2RP[1:0] PE2TN[1:0] PE2TP[1:0] PE4RN[1:0] PE4RP[1:0] PE4TN[1:0] PE4TP[1:0] PE6RN[1:0] PE6RP[1:0] PE6TN[1:0] PE6TP[1:0] PEREFCLKP[0] PEREFCLKN[0] REFCLKM Signal MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT © 2009 Integrated Device Technology, Inc Type Name/Description I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0 ...
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... IDT 89HPES10T4BG2 Data Sheet Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[11] © 2009 Integrated Device Technology, Inc Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 ...
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... IDT 89HPES10T4BG2 Data Sheet Signal CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT SWMODE[2:0] Signal JTAG_TCK JTAG_TDI © 2009 Integrated Device Technology, Inc Type Name/Description I Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices ...
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... IDT 89HPES10T4BG2 Data Sheet Signal JTAG_TDO JTAG_TMS JTAG_TRST_N Signal REFRES0 REFRES2 REFRES4 REFRES6 V CORE PEA DD V PEHA DD V PETA © 2009 Integrated Device Technology, Inc Type Name/Description O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller ...
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... IDT 89HPES10T4BG2 Data Sheet Pin Characteristics Note: Some input pads of the PES10T4BG2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption ...
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... IDT 89HPES10T4BG2 Data Sheet Function EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N SerDes Reference REFRES0 Resistors REFRES2 REFRES4 REFRES6 1. Internal resistor values under typical operating conditions are 92K Ω for pull-up and 90K Ω for pull-down. 2. All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media. ...
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... IDT 89HPES10T4BG2 Data Sheet Logic Diagram — PES10T4BG2 Reference Clocks Reference Clock Frequency Selection PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 4 PCI Express Switch SerDes Input Port 6 MSMBADDR[4:1] Master SMBus Interface ...
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... IDT 89HPES10T4BG2 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter Description Refclk Input reference clock frequency range FREQ T Rising edge rate C-RISE T Falling edge rate C-FALL V Differential input high voltage ...
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... IDT 89HPES10T4BG2 Data Sheet Parameter T Maximum time to transition to a valid Idle after sending TX-IDLE-SET-TO-IDLE an Idle ordered set T Maximum time to transition from valid idle to diff data TX-IDLE-TO-DIFF- DATA T Transmitter data skew between any 2 lanes TX-SKEW T Minimum Instantaneous Lone Pulse Width ...
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... IDT 89HPES10T4BG2 Data Sheet Signal JTAG JTAG_TCK 1 JTAG_TMS , JTAG_TDI JTAG_TDO JTAG_TRST_N 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state ...
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... IDT 89HPES10T4BG2 Data Sheet Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PEA PCI Express Analog Power PEHA PCI Express Analog High Power DD V PETA PCI Express Transmitter Analog Voltage DD V Common ground SS 1 ...
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... IDT 89HPES10T4BG2 Data Sheet Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below) ...
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... IDT 89HPES10T4BG2 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Serial Link PCIe Transmit V Differential peak-to-peak output TX-DIFFp-p voltage V Low-Drive Differential Peak to TX-DIFFp-p-LOW ...
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... IDT 89HPES10T4BG2 Data Sheet I/O Type Parameter Description Serial Link PCIe Receive (cont.) V Differential input voltage (peak-to- RX-DIFFp-p peak) RL Receiver Differential Return Loss RX-DIFF RL Receiver Common Mode Return RX-CM Loss Z Differential input impedance (DC) RX-DIFF- common mode impedance RX--DC Z Powered down input common RX-COMM-DC ...
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... IDT 89HPES10T4BG2 Data Sheet Package Pinout — 324-BGA Signal Pinout for PES10T4BG2 The following table lists the pin numbers and signal names for the PES10T4BG2 device. Pin Function Alt Pin A1 V B17 B18 SS A3 PE0RN00 C1 A4 PE0RP00 ...
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... IDT 89HPES10T4BG2 Data Sheet Pin Function Alt Pin H11 V CORE K13 DD H12 V K14 SS H13 V K15 SS H14 V PEHA K16 DD H15 V CORE K17 DD H16 PE4TN01 K18 H17 H18 PE4RN01 PETA REFRES2 CORE ...
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... IDT 89HPES10T4BG2 Data Sheet Pin Function Alt Pin K12 V M14 U10 U11 SS U3 SSMBCLK U12 U4 SSMBADDR_3 U13 U5 V U14 SS U6 MSMBCLK U15 U7 MSMBADDR_1 U16 U8 V PEA U17 U18 SS Alternate Signal Functions No Connection Pins © 2009 Integrated Device Technology, Inc ...
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... IDT 89HPES10T4BG2 Data Sheet Power Pins V Core DD B14 D8 D9 D12 E5 E10 E13 F4 F7 F12 F14 H11 H15 J5 J9 J12 © 2009 Integrated Device Technology, Inc V Core V I/O V PEA K10 E6 B10 K14 E12 B16 L4 E14 C7 L12 F5 D11 M7 F15 ...
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... IDT 89HPES10T4BG2 Data Sheet Ground Pins A11 A14 B12 B13 B15 C4 C9 C15 D1 D7 D13 © 2009 Integrated Device Technology, Inc K12 E17 H8 K13 F1 H9 K15 F6 H10 K18 F8 H12 L1 F9 H13 ...
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... IDT 89HPES10T4BG2 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_11 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE No Connection © 2009 Integrated Device Technology, Inc I/O Type Location ...
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... IDT 89HPES10T4BG2 Data Sheet Signal Name PE0RN00 PE0RN01 PE0RN02 PE0RN03 PE0RP00 PE0RP01 PE0RP02 PE0RP03 PE0TN00 PE0TN01 © 2009 Integrated Device Technology, Inc I/O Type Location A12 I A15 A13 I A16 Table 23 89PES10T4BG2 Alphabetical Signal List (Part ...
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... IDT 89HPES10T4BG2 Data Sheet Signal Name PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE2RN00 PE2RN01 PE2RP00 PE2RP01 PE2TN00 PE2TN01 PE2TP00 PE2TP01 PE4RN00 PE4RN01 PE4RP00 PE4RP01 PE4TN00 PE4TN01 PE4TP00 PE4TP01 PE6RN00 PE6RN01 PE6RP00 PE6RP01 PE6TN00 PE6TN01 PE6TP00 PE6TP01 PEREFCLKN0 PEREFCLKP0 PERSTN REFCLKM © 2009 Integrated Device Technology, Inc ...
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... IDT 89HPES10T4BG2 Data Sheet Signal Name REFRES0 REFRES2 REFRES4 REFRES6 RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 V CORE PEA PETA © 2009 Integrated Device Technology, Inc I/O Type Location I/O D10 I/O J4 I/O K17 I D14 I P4 ...
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... IDT 89HPES10T4BG2 Data Sheet PES10T4BG2 Pinout — Top View Core (Power I/O (Power) DD Vss (Ground) © 2009 Integrated Device Technology, Inc ...
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... IDT 89HPES10T4BG2 Data Sheet PES10T4BG2 Package Drawing — 324-Pin BC324/BCG324 © 2009 Integrated Device Technology, Inc *Notice: The information in this document is subject to change without notice July 1, 2009 ...
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... IDT 89HPES10T4BG2 Data Sheet PES10T4BG2 Package Drawing — Page Two © 2009 Integrated Device Technology, Inc *Notice: The information in this document is subject to change without notice July 1, 2009 ...
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... IDT 89HPES10T4BG2 Data Sheet Revision History July 1, 2009: Initial publication of Advance data sheet. © 2009 Integrated Device Technology, Inc *Notice: The information in this document is subject to change without notice July 1, 2009 ...
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... IDT 89HPES10T4BG2 Data Sheet Ordering Information NN A NNANA Product Operating Product Family Voltage Detail Valid Combinations 89H10T4BG2ZABC 324-ball BGA package, Commercial Temperature 89H10T4BG2ZABCG 324-ball Green BGA package, Commercial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 ® DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’ ...