80ksbr201 Integrated Device Technology, 80ksbr201 Datasheet - Page 5

• Manufacturer Part Number: 80ksbr201
• Description: High-speed Serial Rapidio 1x Or 4x Lanes Up To 10 Gbps High Speed Buffer. Expandable To 90mb With The Addition Of External Qdr Sram
• Manufacturer: Integrated Device Technology

„2007 Integrated Device Technology, Inc. All rights reserved.
IDT
Notes
data for its own use.
offloading of data.
2.3.2 sRIO to sRIO Buffer
to the SerB or read data from the SerB in the active protocol. No command translation is performed or required. Each port
will handle all link negotiations, responses, and transfers needed for the active protocol. Packet ready flags may be used to
indicate the presence of data within the buffer.
aware of the device on S-Port 2 (or P-Port).
In
The simplest form of translation is where both ports regard the SerB as an end-point memory. Each port may write data
This is similar to the sRIO translation configuration except the SerB isolates the two ports. The device on S-Port 1 is not
Figure 5
above, the SerB acts as a simple FIFO buffer between the two devices with no ability for FPGA to offload
Speed
Speed
Serial
Serial
Lines
Lines
High
High
Speed
Speed
Serial
Serial
Lines
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High
High
Figure 6
sRIO
Figure 6. SerB as a combined FIFO and Offload Device for an FPGA
sRIO
below is similar, except each FPGA has a path within the SerB back to itself allowing the
Figure 5. SerB as a FIFO between two FPGAs
5 of 7
Queue 4
Queue 5
Queue 6
Queue 7
Queue 0
Queue 1
Queue 2
Queue 3
Interface
Queue 4
Queue 1
External
Memory
Interface
External
Memory
sRIO
sRIO
Flags
MRS
CNTL
High
Speed
Serial
Lines
High
Speed
Serial
Lines
November 26, 2007
High
Speed
Serial
Lines
High
Speed
Serial
Lines
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