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... This document contains information on a product under development at Spansion LLC. The information is intended to help you evaluate this product. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice. Flash Memory Density 512 Mb 256 Mb 128 S71GL512NB0 S71GL256NB0 16 Mb Revision A Amendment 1 ADVANCE INFORMATION 128 Mb S71GL128NB0 Issue Date December 7, 2004 ...
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... MCP Block Diagram (512Mb Flash + 32Mb pSRAM) ..................................6 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7 512 Mb Flash + 32 Mb pSRAM Pinout .............................................................7 256 Mb Flash + 32 Mb pSRAM Pinout ............................................................8 128 Mb Flash + 32 Mb pSRAM Pinout .............................................................9 128 Mb Flash + 32 Mb pSRAM Pinout (S71GL128NB0 Only) .................. 10 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 11 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 12 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 16 S29GLxxxN MirrorBit TM Datasheet ...
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Read-Only Operations–S29GL512N Only ..................................................80 Read-Only Operations–S29GL256N Only .................................................. 81 Read-Only Operations–S29GL128N Only .................................................. 82 Figure 11. Read Operation Timings....................................... 83 Figure 12. Page Read Timings.............................................. 83 Hardware Reset (RESET#) .............................................................................. 84 Figure 13. ...
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... Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page Access Time (t Max. OE# Access Time (ns S71GL512NB0 = 2.7 - 3.1 V 100 100 ) PACC S71GL256NB0 = 2 PACC S71GL128NB0 = 2 PACC Flash pSRAM 105 65 105 Flash pSRAM 100 ...
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MCP Block Diagram (128Mb Flash + 32Mb pSRAM Flash-only Address Shared Address WP#/ACC CE#F1 OE# WE# RESET UB#s LB#s CE2s CE1#s MCP Block Diagram (256Mb Flash + ...
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MCP Block Diagram (512Mb Flash + 32Mb pSRAM Flash-only Address Shared Address WP#/ACC CE#F1 OE# WE# RESET UB#s LB#s CE2s CE1 ...
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Connection Diagrams 512 Mb Flash + 32 Mb pSRAM Pinout RFU RFU C3 C2 RFU ...
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Mb Flash + 32 Mb pSRAM Pinout RFU RFU C2 C3 RFU CE#f1 OE# J2 ...
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128 Mb Flash + 32 Mb pSRAM Pinout RFU RFU C2 C3 RFU ...
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... Mb Flash + 32 Mb pSRAM Pinout (S71GL128NB0 Only VSS H2 H3 CE#f OE CE1#s DQ0 K3 DQ8 M1 NC Note: Ball L5 (RFU 84-ball package; therefore recommended that L5 not be connected ...
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Input/Output Descriptions A24-A0 A23-A0 A22-A0 DQ15-DQ0 OE# WE RESET# WP#/ACC CE1#s, CE2s CE# UB#s LB#s RFU RY/BY# Logic Symbol Max+1 December 7, 2004 S71GL512_256_128NB0_00_A1 ...
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Ordering Information The order number (Valid Combination) is formed by the following: S71GL 512 ...
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S71GL512NB0 Valid Combinations Package Base Package & Modifier/ Ordering Temperature Model Part Number Number S71GL512NB0 BAW S71GL512NB0 BFW ...
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S71GL256NB0 Valid Combinations Package Base Package & Modifier/ Ordering Temperature Model Part Number Number S71GL256NB0 BAW S71GL256NB0 BFW Notes: 1. Type 0 is standard. ...
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... S71GL128NB0 Valid Combinations Package Base Package & Modifier/ Ordering Temperature Model Part Number Number S71GL128NB0 BAW S71GL128NB0 BFW Notes: 1. Type 0 is standard. Specify other options as required. ...
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Physical Dimensions TLD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 9.0 x 12.0 x1.2 mm MCP Compatible Package D 0.15 C (2X) INDEX MARK PIN A1 CORNER 10 TOP VIEW SIDE VIEW 6 b 84X 0. ...
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TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 11.6 x1.2 mm MCP Compatible Package D 0.15 C (2X) INDEX MARK PIN A1 CORNER 10 TOP VIEW SIDE VIEW 6 b ...
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TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 11.6 x1.2 mm MCP Compatible Package 0.15 C (2X) INDEX MARK PIN A1 CORNER 10 TOP VIEW SIDE VIEW 6 b 64X 0. 0.08 M ...
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S29GLxxxN MirrorBit TM S29GL512N, S29GL256N, S29GL128N 512 Megabit, 256 Megabit, and 128 Megabit, 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit process technology Datasheet Distinctive Characteristics Architectural Advantages Single power supply operation — 3 volt read, erase, and ...
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General Description The GL512/256/128N family of devices are 3.0V single power flash memory man- ufactured using 110 nm MirrorBit technology. The GL512N is a 512 Mbit, organized as 33,554,432 words or 67,108,864 bytes. The GL256N is a 256 Mbit, organized ...
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The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. The Write Protect ...
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Block Diagram RY/BY RESET# WE# State WP#/ACC Control BYTE# Command Register CE# OE# V Detector CC A **–A0 Max June 14, 2004 S29GLxxxN_00A4 ...
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Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory ...
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The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode ...
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Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing ...
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Current is reduced for the duration of the RESET# pulse. When RESET# is held at V ±0.3 V, the ...
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Table 2. Sector Address Table–S29GL256N (Continued) Sector A23–A16 SA23 SA24 SA25 SA26 SA27 ...
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Table 2. Sector Address Table–S29GL256N (Continued) Sector A23–A16 SA58 SA59 SA60 SA61 SA62 SA63 0 ...
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Table 2. Sector Address Table–S29GL256N (Continued) Sector A23–A16 SA93 SA94 SA95 SA96 SA97 ...
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Table 2. Sector Address Table–S29GL256N (Continued) Sector A23–A16 SA128 SA129 SA130 SA131 SA132 SA133 1 ...
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Table 2. Sector Address Table–S29GL256N (Continued) Sector A23–A16 SA163 SA164 SA165 SA166 SA167 ...
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Table 2. Sector Address Table–S29GL256N (Continued) Sector A23–A16 SA198 SA199 SA200 SA201 SA202 SA203 1 ...
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Table 2. Sector Address Table–S29GL256N (Continued) Sector A23–A16 SA233 SA234 SA235 SA236 SA237 ...
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Table 3. Sector Address Table–S29GL128N (Continued) Sector A22–A16 SA7 SA8 SA9 SA10 SA11 SA12 SA13 0 ...
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Table 3. Sector Address Table–S29GL128N (Continued) Sector A22–A16 SA42 SA43 SA44 SA45 SA46 ...
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Table 3. Sector Address Table–S29GL128N (Continued) Sector A22–A16 SA77 SA78 SA79 SA80 SA81 SA82 SA83 0 ...
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Table 3. Sector Address Table–S29GL128N (Continued) Sector A22–A16 SA112 SA113 SA114 SA115 SA116 ...
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Persistent Sector Protection. If the customer decides to use the password method, they must set the Password Mode Locking Bit. This will permanently set the part to operate only using password sector protection important to ...
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Persistent Protection Mode Lock Bit allows the user to set the device perma- nently to operate in the Persistent Protection Mode Password Protection Mode Lock Bit allows the user to set the device ...
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Setting the PPB Lock Bit to the “freeze state” disables all program and erase commands to the Non-Volatile PPB bits. In effect, the PPB Lock Bit locks the PPB bits into their current state. The only way to clear ...
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Persistent Protection Bit Lock (PPB Lock Bit) A global volatile bit. When set to the “freeze state”, the PPB bits cannot be changed. When cleared to the “unfreeze state”, the PPB bits are ...
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Password Protection Mode Lock Bit. This guarantees that a hacker could not place the device in Password Protection Mode. The Password Protection Mode Lock Bit resides in the “Lock Register”. Password Sector Protection The Password Sector Protection method allows ...
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Lock Bit, there will be no way to clear and unfreeze the PPB Lock Bit. The Pass- word Protection Mode Lock Bit, once programmed, prevents reading the 64-bit password on the DQ bus ...
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Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled. The Secured Silicon sector address space in this device is allocated as follows: Secured Silicon ...
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shipped from the factory with the Secured Silicon Sector permanently locked. Contact your sales representative for details on using the ExpressFlash service. Write Protect (WP#) The Write Protect function provides a hardware method ...
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The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft- ware algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and ...
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Addresses (x16) Data 10h 0051h 11h 0052h 12h 0059h 13h 0002h 14h 0000h 15h 0040h 16h 0000h 17h 0000h 18h 0000h 19h 0000h 1Ah 0000h Addresses (x16) Data 1Bh 0027h 1Ch 0036h 1Dh ...
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Addresses (x16) Data 001Ah 27h 0019h 0018h 28h 0002h 29h 0000h 2Ah 0005h 2Bh 0000h 2Ch 0001h 2Dh 00xxh 2Eh 000xh 2Fh 0000h 30h 000xh 31h 0000h 32h 0000h 33h 0000h 34h 0000h 35h 0000h 36h 0000h 37h 0000h 38h ...
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Table 9. Primary Vendor-Specific Extended Query Addresses (x16) Data 40h 0050h 41h 0052h 42h 0049h 43h 0031h 44h 0033h 45h 0010h 46h 0002h 47h 0001h 48h 0000h 49h 0008h 4Ah 0000h 4Bh 0000h ...
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Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After ...
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address that is either in the read or erase-suspend-read mode. The autose- lect command may not be written while the device is actively programming or erasing. The autoselect command sequence is ...
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DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” “1.” Unlock Bypass Command Sequence The unlock bypass feature allows ...
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than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Program ...
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Write “Write to Buffer” command and Sector Address Write number of addresses to program minus 1(WC = 31) and Sector Address Write first address/data Yes Abort Write to Buffer Operation? Write next address/data pair WC = ...
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Note: mand sequence. Program Suspend/Program Resume Command Sequence The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read ...
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After the Program Resume command is written, the device reverts to program- ming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Op- ...
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Any commands written during the chip erase operation are ignored, including erase suspend commands. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence ...
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Notes: 1. See Table sequence. 2. See the section on DQ3 for information on the sector erase timer. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data ...
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gram operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system ...
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The Password Program command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. There is no special addressing order required for programming the pass- word. The password is programmed ...
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The Password Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Otherwise the device will hang. Note that issuing ...
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Reads and writes from the main memory are allowed. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock Bit to the “freeze state” cleared either at reset or ...
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Read from Secured Silicon Sector Program to Secured Silicon Sector Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command has to be issued to exit Secured Silicon ...
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Command Definitions Table 10. S29GL512N, S29GL256N, S29GL128N Command Definitions, x16 Command (Notes) Read (6) Reset (7) Manufacturer ID Device ID Sector Protect Verify Secure Device Verify (9) CFI Query (11) Program Write to Buffer Program Buffer to Flash (confirm) Write-to-Buffer-Abort ...
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Command (Notes) Password Protection Command Set Entry Password Program (20) Password Read (19) Password Unlock (19) Password Protection Command Set Exit (18, 23) Non-Volatile Sector Protection Command Set Definitions Nonvolatile Sector Protection Command ...
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WC = Word Count is the number of write buffer locations to load minus 1. PWD = Password PWD = Password word0, word1, word2, and word3. x DATA = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit, PD(1) ...
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Table 11. S29GL512N, S29GL256N, S29GL128N Command Definitions, x8 Command (Notes) Read (6) Reset (7) Manufacturer ID Device ID Sector Protect Verify Secure Device Verify (9) CFI Query (11) Write to Buffer Program Buffer ...
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Command (Notes) Password Protection Command Set Entry Password Program (20) Password Read (19) Password Unlock (19) Password Protection Command Set Exit (18, 23) Non-Volatile Sector Protection Command Set Definitions Nonvolatile Sector Protection Command Set Entry PPB Program (24, 25) All ...
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Address of the sector to be verified (in autoselect mode) or erased. Address bits A WBL = Write Buffer Location. The address must be within the same write buffer page as ...
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The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. Note that all Write Operation Status DQ bits are valid only after 4 µs delay. ...
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Notes Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any ...
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DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any ...
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ing diagrams. Figure 19 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. Note: The system should recheck the toggle bit even if ...
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DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing ...
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DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to de- termine whether or not erasure has begun. (The sector erase timer does not apply to ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Program-Suspended Program Program- Sector Suspend Suspend Non-Program Mode Read Suspended Sector Erase-Suspended Erase- Sector Suspend Erase Non-Erase Read Suspend Suspended Sector Mode Erase-Suspend-Program (Embedded Program) Busy (Note 3) Write-to- Buffer Abort ...
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the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for ...
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DC Characteristics CMOS Compatible Parameter Parameter Description Symbol (Notes) I Input Load Current ( Input Load Current LIT I Output Leakage Current LO V Active Read Current IO I IO1 (Switching Current Non-Active Output IO2 ...
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Test Conditions Device Under Test C L 6.2 kΩ Note: Diodes are IN3064 or equivalent. Figure 9. Test Setup Note: Diodes are IN3064 or equivalent Note < the reference ...
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AC Characteristics Read-Only Operations–S29GL512N Only Parameter JEDEC Std. Description t AVAV t Read Cycle Time RC Address to Output Delay t t AVQV ACC (Note 2) Chip Enable to Output Delay t t ELQV CE (Note 3) t PAC Page ...
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Characteristics Read-Only Operations–S29GL256N Only Parameter JEDEC Std. Description t t Read Cycle Time AVAV Address to Output Delay (Note 2) AVQV ACC Chip Enable to Output Delay t t ...
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AC Characteristics Read-Only Operations–S29GL128N Only Parameter JEDEC Std. Description t t Read Cycle Time AVAV Address to Output Delay (Note 2) AVQV ACC t t Chip Enable to Output Delay (Note 3) ELQV CE t PAC Page ...
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Characteristics Addresses CE# OE# WE# Outputs RESET# RY/BY A23-A2 A1-A0* Data Bus CE# OE# Note:Figure shows word mode. Addresses are A2–A-1 for byte mode. June 14, 2004 S29GLxxxN_00_A4 I n ...
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AC Characteristics Hardware Reset (RESET#) Parameter JEDEC Std. RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width RP ...
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Characteristics Erase and Program Operations–S29GL512N Only Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS Address Setup Time to OE# low ...
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AC Characteristics Erase and Program Operations–S29GL256N Only Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS Address Setup Time to OE# low during toggle t ASO bit polling t ...
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Characteristics Erase and Program Operations–S29GL128N Only Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS Address Setup Time to OE# low ...
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AC Characteristics Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data Illustration shows device in word ...
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Characteristics Erase Command Sequence (last two cycles Addresses 2AAh CE Data RY/BY# t VCS V CC Notes sector address (for Sector ...
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AC Characteristics Addresses CE OE# t OEH WE# DQ15 and DQ7 DQ14–DQ8, DQ6–DQ0 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle ...
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Characteristics Addresses CE# t OEH WE# OE Valid Data DQ6 & DQ14/ DQ2 & DQ10 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status ...
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AC Characteristics Alternate CE# Controlled Erase and Program Operations–S29GL512N Only Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX Data ...
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Characteristics Alternate CE# Controlled Erase and Program Operations–S29GL256N Only Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address ...
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AC Characteristics Alternate CE# Controlled Erase and Program Operations–S29GL128N Only Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX Data ...
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Characteristics 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a ...
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Erase And Programming Performance Parameter Sector Erase Time S29GL128N Chip Erase Time S29GL256N S29GL512N Total Write Buffer Time (Note 3) Total Accelerated Effective Write Buffer Programming Time (Note 3) S29GL128N Chip Program Time S29GL256N S29GL512N Notes: 1. Typical program and ...
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pSRAM Type 1 4Mbit (256K Word x 16-bit) 8Mbit (512K Word x 16-bit) 16Mbit (1M Word x 16-bit) 32Mbit (2M Word x 16-bit) 64Mbit (4M Word x 16-bit) Functional Description Mode CE# CE2/ZZ# ...
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DC Characteristics (4Mb pSRAM Asynchronous) Symbol Parameter V Power Supply CC V Input High Level IH V Input Low Level IL Input Leakage I IL Current Output Leakage I LO Current Output High V OH Voltage Output Low V OL ...
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Characteristics (8Mb pSRAM Asynchronous) Version Performance Grade Density Symbol Parameter Conditions V Power Supply CC V Input High Level IH V Input Low Level IL Input Leakage I Vin = 0 to ...
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DC Characteristics (16Mb pSRAM Asynchronous) Symbol Parameter V Power Supply CC V Input High Level IH V Input Low Level IL I Input Leakage Current IL I Output Leakage Current LO V Output High Voltage OH V Output Low Voltage ...
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Characteristics (16Mb pSRAM Page Mode) Performance Grade Density Symbol Parameter Conditions V Power Supply CC Input High V IH Level Input Low V IL Level Input Leakage I Vin = 0 to ...
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DC Characteristics (32Mb pSRAM Page Mode) Version Performance Grade Density Symbol Parameter Conditions Power V CC Supply Input High V IH Level Input Low V IL Level Input I Leakage Vin = Current Output OE ...
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Characteristics (64Mb pSRAM Page Mode) Symbol Parameter V Power Supply CC V Input High Level IH V Input Low Level IL Input Leakage I IL Current Output Leakage I LO Current Output ...
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Output Load Circuit Power Up Sequence After applying power, maintain a stable power supply for a minimum of 200 µs after CE# > 104 ...
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Characteristics (4Mb pSRAM Page Mode) 3 Volt August 30, 2004 pSRAM_Type01_12_A1 Asynchronous Performance Grade -70 Density 4Mb pSRAM Symbol Parameter Min ...
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Volt 106 Asynchronous Performance Grade -70 Density 4Mb pSRAM Symbol Parameter Min Max twc Write cycle time 70 Chipselect to end ...
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Characteristics (8Mb pSRAM Asynchronous) Version Performance Grade Density 3 Volt Symbol Parameter trc Read cycle time Address Access taa Time Chip select to tco output Output enable to toe valid output UB#, ...
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Version Performance Grade Density 3 Volt Symbol Parameter twc Write cycle time Chip select to tcw end of write Address set up tas Time Address valid to taw end of write UB#, LB# valid tbw to end of write twp ...
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Characteristics (16Mb pSRAM Asynchronous) Performance Grade 3 Volt Symbol trc taa tco toe tba tlz tblz tolz thz tbhz tohz toh August 30, 2004 pSRAM_Type01_12_A1 ...
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Performance Grade 3 Volt Symbol twc tcw tas taw tbw twp twr twhz tdw tdh tow tow tpc tpa twpc tcp 110 ...
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Characteristics (16Mb pSRAM Page Mode) Performance Grade Density 3 Volt Symbol Parameter trc Read cycle time Address Access taa Time Chip select to tco output Output enable to toe valid output UB#, ...
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Performance Grade Density 3 Volt Symbol Parameter twc Write cycle time Chipselect to end tcw of write Address set up tas Time Address valid to taw end of write UB#, LB# valid tbw to end of write twp Write pulse ...
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Characteristics (32Mb pSRAM Page Mode) Version Performance Grade Density 3 Volt Symbol Parameter trc Read cycle time Address Access taa Time Chip select to tco output Output enable to toe valid output ...
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Version Performance Grade Density 3 Volt Symbol Parameter twc Write cycle time Chipselect to end tcw of write Address set up tas Time Address valid to taw end of write UB#, LB# valid tbw to end of write twp Write ...
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Characteristics (64Mb pSRAM Page Mode) 3 Volt August 30, 2004 pSRAM_Type01_12_A1 Page Mode Performance Grade -70 Density 64Mb pSRAM Symbol Parameter ...
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Volt Timing Diagrams Read Cycle Address Previous Data Valid Data Out Figure 22. Timing of Read Cycle (CE 116 ...
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Address CE# OE# LB#, UB# High-Z Data Out Figure 23. Timing Waveform of Read Cycle (WE August 30, 2004 pSRAM_Type01_12_A1 ...
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Page Address (A4 - A20) Word Address (A0 - A3) CE# OE# LB#, UB# High-Z Data Out Figure 24. Timing Waveform of Page Mode Read Cycle (WE 118 ...
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Write Cycle Addr es s CE# LB#, UB# WE# High-Z Dat Out Figure 25. Timing Waveform of Write Cycle (WE# Control, ZZ dres s CE# LB#, ...
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Page A ddr 20) Wor d A ddr CE# WE# LB#, UB# High-Z Dat a Out Figure 27. Timing Waveform of Page Mode Write Cycle (ZZ# = ...
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freshed. The data in the remainder of the array will be lost. The PASR operation mode is only available during standby time (ZZ# low) and once ZZ# is returned high, the device resumes ...
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A21 - A8 A7 Reserved Must set to all 0 Page Mode 0 = Page Mode Disabled (default Page Mode Enabled Address CE# WE# t CDZZ ZZ# Figure 29. Mode Register UpdateTimings (UB#, LB#, OE# are Don’t Care) ...
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ZZ# t CDZZ CE# Figure 30. Deep Sleep Mode - Entry/Exit Timings (for 64M CE# WE# LB#, UB# t ZZWE ZZ# Figure 31. Deep Sleep Mode - Entry/Exit Timings (for ...
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Address Patterns for PASR (A4=1) (64M Active Section Top quarter of die Top half of die Reserved PASR Bottom quarter of ...
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Address Patterns for RMS ( (32M Active Section One-quarter of die One-half of die One-quarter of ...
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Low Power ICC Characteristics (32M) Item Symbol PAR Mode Standby Current I PAR RMS Mode Standby Current I RMSSB Deep Sleep Current I ZZ Address Patterns for PAR (A3= 0, A4=1) (16M Active Section ...
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pSRAM Type 7 16Mb (1M word x 16-bit) 32Mb (2M word x 16-bit) 64Mb (4M word x 16-bit) CMOS 1M/2M/4M-Word x 16 bit Fast Cycle Random Access Memory with Low Power SRAM Interface ...
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Pin Name V Ground SS Functional Description Mode CE2# Standby (Deselect) H Output Disable (Note 1) Output Disable (No Read) Read (Upper Byte) Read (Lower Byte) Read (Word Write Write (Upper Byte) Write (Lower Byte) Write (Word) Power ...
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The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2 is brought to Low for Power Down not required to program ...
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Absolute Maximum Ratings Item Voltage of V Supply Relative Voltage at Any Pin Relative Short Circuit Output Current Storage temperature WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, ...
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Characteristics (Under Recommended Conditions Unless Otherwise Noted) Parameter Symbol Input Leakage Current Output Leakage OUT I LO Current Disable Output High V = ...
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AC Characteristics (Under Recommended Operating Conditions Unless Otherwise Noted) Read Operation Parameter Symbol Read Cycle Time t RC CE1# Access Time t CE OE# Access Time t OE Address Access Time t AA LB# / UB# Access Time t BA ...
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Applicable A21 (32M and 64M) when CE1# is kept at Low. 6. Applicable only to A0, A1 and A2 (32M and 64M) when CE1# is kept at Low for ...
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AC Characteristics Write Operation Parameter Symbol Write Cycle Time t WC Address Setup Time t AS CE1# Write Pulse Width t CW WE# Write Pulse Width t WP LB#/UB# Write Pulse Width t BW LB#/UB# Byte Mask Setup t BS ...
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Characteristics Power Down Parameters Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1# High Hold Time following CE2 High after Power Down Exit ...
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AC Characteristics AC Test Conditions Symbol Description V Input High Level IH V Input Low Level IL V Input Timing Measurement Level REF t Input Transition Time T AC Measurement Output Load Circuit V DD 0.1µ 136 A ...
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Timing Diagrams Read Timings ADDRESS t ASC CE1# OE# LB#/ UB# DQ (Output) Note: This timing diagram assumes CE2=H and WE#=H. ADDRESS ADDRESS VALID CE1# Low t ASO OE# LB#/UB# DQ (Output) Figure ...
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AX ADDRESS t AA Low CE1#, OE# t LB# UB# DQ1-8 (Output) DQ9-16 (Output) Figure 35. Read Timing #3 (LB#/UB# Byte Access) Note: This timing diagram assumes CE2=H and WE#=H. ADDRESS (A21-A3 ADDRESS ADDRESS VALID (A2-A0) t ...
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ADDRESS ADDRESS VALID (A21-A3 ADDRESS ADDRESS VALID (A2-A0 CE1# Low t t ASO OE OE LB#/UB# t OLZ t BLZ DQ (Output) Figure 37. Read Timing #5 ...
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ADDRESS t OHAH CE1# Low t AS WE# LB#, UB# t OES OE# t OHZ DQ (Input) Figure 39. Write Timing #2 (WE# Control) Note:This timing diagram assumes CE2=H. ADDRESS CE1# Low t AS WE# LB UB# DQ1-8 ...
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ADDRESS CE1# Low WE LB UB# DQ1-8 (Input) DQ9-16 (Input) Figure 41. Write Timing #3-2 (WE#/LB#/UB# Byte Write Control) Note: This timing diagram assumes CE2=H and OE#=H. ADDRESS CE1# ...
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ADDRESS CE1# Low WE LB# DQ1-8 (Input UB# DQ9-16 (Input) Figure 43. Write Timing #3-4 (WE#/LB#/UB# Byte Write Control) Note: This timing diagram assumes CE2=H and OE#=H. Read/Write Timings ADDRESS t t CHAH AS CE1# t ...
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ADDRESS t t CHAH AS CE1 WE# UB#, LB# t OHCL OE# t CHZ READ DATA OUTPUT Figure 45. Read / Write Timing #1-2 (CE1#/WE#/OE# Control) Notes: 1. ...
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ADDRESS t CE1# OHAH Low WE OES AS UB#, LB# t BHZ OE READ DATA OUTPUT Figure 47. Read / Write Timing #3 (OE#, WE#, LB#, UB# Control) Notes: 1. This timing diagram assumes CE2=H. ...
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CE1# CE2 Note: The t specifies after V reaches specified minimum level and applicable to both CE1# and CE2. CHH DD CE1# CE2 t CSP DQ Power Down Entry Figure ...
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RC MSB* 1 ADDRESS t CP CE1# OE# WE# LB#, UB# DQ* RDa 3 Cycle #1 Figure 52. Power Down Program Timing (for 32M/64M Only) Notes: 1. The all address inputs must be High from Cycle #1 to #5. ...
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Revision Summary Revision A (August 24, 2004) Initial release. Revision A1 (December 7, 2004) Connection Diagrams. Added 64-ball pinout. Ordering Information Updated the OPN table. Valid Combinations tables Updated all tables. Colophon The ...