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S71GS256/128N based MCPs Stacked Multi-Chip Product (MCP) 256/128 Megabit (16/8M x 16-bit) CMOS 3.0 Volt MirrorBit Uniform Sector Page-mode Flash IO Memory with 64/32 Megabit (4/2M x 16-bit) 1.8V pSRAM Data Sheet Distinctive Characteristics MCP ...
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Product Selector Guide Speed/Voltage Option Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page Access Time (tpacc) Max. OE# Access Time (ns) Speed/Voltage Option Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page Access Time (tpacc) ...
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S71GS256/128N based MCPs General Description . . . . . . . . . . . . . . . . . . . . . . . . 1 Product Selector Guide ...
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Read-Only Operations–S29GL128N, S29GL256N, S29GL512N .......... 92 Figure 11. Read Operation Timings....................................... 93 Figure 12. Page Read Timings.............................................. 93 Hardware Reset (RESET#) .............................................................................. 94 Figure 13. Reset Timings..................................................... 94 Erase and Program Operations–S29GL128N, S29GL256N, S29GL512N ...................................................................................95 Figure 14. Program Operation Timings.................................. ...
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Table 44. Asynchronous WRITE Timing Parameters—CE# -Controlled .............................................147 Figure 49. LB# / UB# -Controlled Asynchronous WRITE........... 149 Table 45. Asynchronous WRITE Timing Parameters—LB#/ UB# - Controlled .......................................................................149 Figure 50. WE# -Controlled Asynchronous WRITE.................. ...
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Figure 82. Extended Timing for t (2) .............................. 194 CEM Impact on Extended WRITE Operations ..................................................194 Figure 83. Extended WRITE Operation ................................ 194 Summary . . . . . . . . . . . . . . . . ...
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MCP Block Diagrams (256 Mb Flash + 64 Mb pSRAM) F-V IO F-V CC Flash-only Address Shared Address WP#/ACC F1-CE# OE# WE# F-RST R-UB# R-LB# ZZ# R-CE1# December 17, 2004 ...
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Mb Flash + 32 Mb pSRAM) F-V IO F-V CC Flash-only Address Shared Address WP#/ACC F1-CE# OE# WE# F-RST# R-V CC R-UB# R-LB# CRE R-CE1 ...
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Connection Diagrams 256 Mb Flash + 64 Mb pSRAM Pinout A1 DNU B2 B3 RFU RFU C3 C2 RFU ...
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Mb Flash + 32 Mb pSRAM Pinout A1 DNU B2 B3 RFU RFU C3 C2 RFU F1-CE# OE# J ...
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Input/Output Descriptions A23-A0 A22-A0 DQ15-DQ0 OE# WE F-RST# WP# / ACC R-CE1# ZZ# CRE F1-CE# F-V CC R-V CC R-UB# R-LB# RFU RY/BY# F-V IO R-V IO December 17, 2004 ...
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Logic Symbol Notes: 1. Max = 24 [256 Mb Flash], 23 [128 Mb Flash]. 2. AMax = A23 [256 Mb Flash], A22 [128 Mb Flash]. 3. CRE is available only in Synchronous pSRAM. 4. ZZ# is available only in Asynchronous ...
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Ordering Information The order number (Valid Combination) is formed by the following: S71GS 256 S71GS256NC0 Valid Combinations Package Base Package & Modifier/ Ordering Temperature Model Part Number Number AK S71GS256NC0 ...
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S71GS128NB0 Valid Combinations Package Base Package & Modifier/ Ordering Temperature Model Part Number Number AK S71GS128NB0 BAW AP AK S71GS128NB0 BFW AP Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” ...
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Physical Dimensions TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 11.6 x1.2 mm MCP Compatible Package 0.15 C (2X) INDEX MARK PIN A1 CORNER 10 TOP VIEW SIDE VIEW 6 ...
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S29GLxxxN MirrorBit S29GL512N, S29GL256N, S29GL128N 512 Megabit, 256 Megabit, and 128 Megabit, 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit process technology Data Sheet Distinctive Characteristics Architectural Advantages T Single power supply operation — 3 volt read, erase, ...
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General Description The S29GL512/256/128N family of devices are 3.0V single power flash memory manufactured using 110 nm MirrorBit technology. The S29GL512N is a 512 Mbit, organized as 33,554,432 words or 67,108,864 bytes. The ...
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A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects ...
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Product Selector Guide S29GL512N Part Number V = 2.7–3 Speed Option V = 3.0-3.6V CC Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page access time (ns) Max. OE# ...
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Block Diagram RY/ BY RESET# WE# State WP#/ ACC Control Command Register CE# OE# V Detector CC A **–A0 Max Notes GL512N = A24, A GL256N = A23, A Max Max 20 ...
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Pin Description A24–A0 A23–A0 A22–A0 DQ14–DQ0 DQ15/A-1 CE# OE# WE# WP#/ACC RESET# RY/BY December 15, 2004 S29GLxxxN_MCP_A1 ...
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Logic Symbol S29GL512N A24– DQ15–DQ0 CE# (A-1) OE# WE# WP#/ ACC RESET# V RY/ BY# ...
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Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory ...
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No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device ...
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the system asserts V mentioned Unlock Bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce the time required for program operations. The ...
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Current is reduced for the duration of the RESET# pulse. When RESET# is held at V ± 0.3 V, the device draws CMOS standby current ( but not within V IL The RESET# pin may be tied ...
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Table 2. Sector Address Table–S29GL512N (Continued) Sector A24–A16 SA24 SA25 SA26 SA27 SA28 ...
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Table 2. Sector Address Table–S29GL512N (Continued) Sector A24–A16 SA59 SA60 SA61 SA62 SA63 SA64 0 ...
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Table 2. Sector Address Table–S29GL512N (Continued) Sector A24–A16 SA94 SA95 SA96 SA97 SA98 ...
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Table 2. Sector Address Table–S29GL512N (Continued) Sector A24–A16 SA129 SA130 SA131 SA132 SA133 SA134 0 ...
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Table 2. Sector Address Table–S29GL512N (Continued) Sector A24–A16 SA164 SA165 SA166 SA167 SA168 ...
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Table 2. Sector Address Table–S29GL512N (Continued) Sector A24–A16 SA199 SA200 SA201 SA202 SA203 SA204 0 ...
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Table 2. Sector Address Table–S29GL512N (Continued) Sector A24–A16 SA234 SA235 SA236 SA237 SA238 ...
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Table 2. Sector Address Table–S29GL512N (Continued) Sector A24–A16 SA269 SA270 SA271 SA272 SA273 SA274 1 ...
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Table 2. Sector Address Table–S29GL512N (Continued) Sector A24–A16 SA304 SA305 SA306 SA307 SA308 ...
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Table 2. Sector Address Table–S29GL512N (Continued) Sector A24–A16 SA339 SA340 SA341 SA342 SA343 SA344 1 ...
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Table 2. Sector Address Table–S29GL512N (Continued) Sector A24–A16 SA374 SA375 SA376 SA377 SA378 ...
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Table 2. Sector Address Table–S29GL512N (Continued) Sector A24–A16 SA409 SA410 SA411 SA412 SA413 SA414 1 ...
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Table 2. Sector Address Table–S29GL512N (Continued) Sector A24–A16 SA444 SA445 SA446 SA447 SA448 ...
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Table 2. Sector Address Table–S29GL512N (Continued) Sector A24–A16 SA479 SA480 SA481 SA482 SA483 SA484 1 ...
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Table 3. Sector Address Table–S29GL256N Sector A23–A16 SA0 SA1 SA2 SA3 SA4 SA5 ...
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Table 3. Sector Address Table–S29GL256N (Continued) Sector A23–A16 SA34 SA35 SA36 SA37 SA38 SA39 SA40 0 ...
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Table 3. Sector Address Table–S29GL256N (Continued) Sector A23–A16 SA69 SA70 SA71 SA72 SA73 ...
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Table 3. Sector Address Table–S29GL256N (Continued) Sector A23–A16 SA104 SA105 SA106 SA107 SA108 SA109 SA110 0 ...
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Table 3. Sector Address Table–S29GL256N (Continued) Sector A23–A16 SA139 SA140 SA141 SA142 SA143 ...
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Table 3. Sector Address Table–S29GL256N (Continued) Sector A23–A16 SA174 SA175 SA176 SA177 SA178 SA179 SA180 1 ...
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Table 3. Sector Address Table–S29GL256N (Continued) Sector A23–A16 SA209 SA210 SA211 SA212 SA213 ...
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Table 3. Sector Address Table–S29GL256N (Continued) Sector A23–A16 SA244 SA245 SA246 SA247 SA248 SA249 SA250 1 ...
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Table 4. Sector Address Table–S29GL128N (Continued) Sector A22–A16 SA18 SA19 SA20 SA21 SA22 ...
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Table 4. Sector Address Table–S29GL128N (Continued) Sector A22–A16 SA53 SA54 SA55 SA56 SA57 SA58 SA59 1 ...
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Table 4. Sector Address Table–S29GL128N (Continued) Sector A22–A16 SA88 SA89 SA90 SA91 SA92 ...
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Table 4. Sector Address Table–S29GL128N (Continued) Sector A22–A16 SA123 SA124 SA125 SA126 SA127 Autoselect Mode The autoselect mode provides manufacturer ...
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Table 5. Autoselect Codes, (High Voltage Method) Description CE# OE# Manufacturer ID Spansion Product Cycle 1 Cycle Cycle 3 Cycle 1 Cycle Cycle 3 Cycle ...
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Persistent Sector Protection method, they must set the Persistent Sector Protection Mode Locking Bit. This will permanently set the part to op- erate only using Persistent Sector Protection. If the customer decides to use the password method, they ...
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Persistent Protection Mode Lock Bit allows the user to set the device perma- nently to operate in the Persistent Protection Mode T Password Protection Mode Lock Bit allows the user to set ...
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The Software Reset command will not clear the PPB Lock Bit to the “unfreeze state”. System boot code can determine if any changes to the PPB bits are ...
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freeze state” after power-up or hardware reset. There is no command sequence to unlock or “unfreeze” the PPB Lock Bit. Configuring the PPB Lock Bit to the freeze state requires approximately 100ns. Reading ...
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Password Sector Protection The Password Sector Protection method allows an even higher level of security than the Persistent Sector Protection method. There are two main differences be- tween the Persistent Sector Protection and the Password Sector Protection methods: T When ...
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programmed, the P ersistent Protection Mode Lock Bit is disabled from program- ming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own ...
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The Secured Silicon sector address space in this device is allocated as follows: Secured Silicon Sector Address Range 000000h–000007h 000008h–00007Fh The system accesses the Secured Silicon Sector through a command sequence (see “Write Protect (WP# )”). After the system has ...
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Write Protect (WP#) The Write Protect function provides a hardware method of protecting the first or last sector group without using V by the WP#/ACC input the system asserts V erase ...
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JEDEC I D-independent, and forward- and back- ward-compat ible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the ...
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Addresses (x16) Data 1Bh 0027h 1Ch 0036h 1Dh 0000h 1Eh 0000h 1Fh 0007h 20h 0007h 21h 000Ah 22h 0000h 23h 0001h 24h 0005h 25h 0004h 26h 0000h December 15, 2004 S29GLxxxN_MCP_A1 I n ...
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Addresses (x16) Data 001Ah 27h 0019h 0018h 28h 0002h 29h 0000h 2Ah 0005h 2Bh 0000h 2Ch 0001h 2Dh 00xxh 2Eh 000xh 2Fh 0000h 30h 000xh 31h 0000h 32h 0000h 33h 0000h 34h 0000h 35h 0000h 36h 0000h 37h 0000h 38h ...
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Table 11. Primary Vendor-Specific Extended Query Addresses (x16) Data 40h 0050h 41h 0052h 42h 0049h 43h 0031h 44h 0033h 45h 0010h 46h 0002h 47h 0001h 48h 0000h 49h 0008h 4Ah 0000h 4Bh 0000h ...
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Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After ...
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address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing. The autoselect command sequence is initiated by first ...
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Spansion representative. Word programming is supported for backward compatibility with existing Flash driver software and for occasional writing of in- dividual words. Use of Write Buffer Programming is strongly recommended for general programming use when more than a few ...
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Note that if a Write Buffer address location is loaded multiple times, the address/ data pair counter will be decremented for every data load operation. The host system must therefore account for loading ...
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V for operations other than accelerated programming, or device damage HH may result. WP# has an internal pullup; when unconnected, WP Figure 2 illustrates the algorithm for the program operation. Refer to the Erase and ...
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Note: Program Suspend/Program Resume Command Sequence The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any ...
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After the Program Resume command is written, the device reverts to program- ming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Op- ...
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Any commands written during the chip erase operation are ignored, including erase suspend commands. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence ...
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Notes: 1. See 2. See the section on DQ3 for information on the sector Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data ...
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gram operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. Refer t o the Write Operat ion Status sect ion for more information the ...
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T Password Program Command T Password Read Command T Password Unlock Command The Password Program command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. There is no special ...
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The Password Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Otherwise the device will hang. Note that issuing ...
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Reads and writes from the main memory are not allowed. T PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock Bit to the “freeze state” cleared either at ...
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Secured Silicon Sector Entry Command The Secured Silicon Sector Entry command allows the following commands to be executed T Read from Secured Silicon Sector T Program to Secured Silicon Sector Once the Secured ...
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Command Definitions Table 12. S29GL512N, S29GL256N, S29GL128N Command Definitions, x16 Command (Notes) Read (6) Reset (7) Manufacturer ID Device ID Sector Protect Verify Secure Device Verify (9) CFI Query (11) Program Write to Buffer Program Buffer to Flash (confirm) Write-to-Buffer-Abort ...
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Command (Notes) Password Protection Command Set Entry Password Program (20) Password Read (19) Password Unlock (19) Password Protection Command Set Exit (18, 23) Non-Volatile Sector Protection Command Set Definitions Nonvolatile Sector Protection Command ...
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WC = Word Count is the number of write buffer locations to load minus 1. PWD = Password PWD = Password word0, word1, word2, and word3. x DATA = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit, PD(1) ...
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Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. tions describe the function of these bits. DQ7 and ...
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Notes Valid address for programming. During a sector 2. DQ7 should be rechecked even if DQ5 = “1” because RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in ...
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DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle ...
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The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. DQ2: ...
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read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing Erase Suspend, but cannot distinguish ...
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When the time-out period is complete, DQ3 switches from a “0” “1.” If the time between additional sector erase commands from the system can be as- sumed ...
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Absolute Maximum Ratings A9, OE# , and ACC (Note –0 ...
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DC Characteristics CMOS Compatible-S29GL128N, S29GL256N, S29GL512N Parameter Parameter Description Symbol (Notes nput Load Current ( Input Load Current LIT I Output Leakage Current Active Read Current (1) CC1 Intra-Page ...
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Test Conditions Device Under Test C L 6.2 kΩ Note: Diodes are IN3064 or equivalent. Figure 9. Test Setup Note < the reference level is 0 ...
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AC Characteristics Read-Only Operations–S29GL128N, S29GL256N, S29GL512N Parameter JEDEC Std. Description t t Read Cycle Time AVAV RC Address to Output Delay t t AVQV ACC (Note 2) Chip Enable to Output Delay t t ELQV CE (Note 3) t Page ...
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Characteristics Addresses CE# OE# WE# Outputs RESET# RY/BY Amax-A2 A2-A0* Data Bus CE# OE# Notes: 1. Figure shows word mode. December 15, 2004 S29GLxxxN_MCP_A1 ...
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AC Characteristics Hardware Reset (RESET#) Parameter JEDEC Std. RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width RP ...
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Characteristics Erase and Program Operations–S29GL128N, S29GL256N, S29GL512N Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS Address Setup Time to OE# ...
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AC Characteristics Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data Illustration shows device in word ...
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Characteristics Erase Command Sequence (last two cycles Addresses 2AAh CE Data RY/BY# t VCS V CC Notes sector address ...
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AC Characteristics t Addresses VA t ACC OE# t OEH WE# DQ7 DQ6–DQ0 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and ...
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Characteristics Addresses CE# t OEH WE# OE Valid Data DQ2 and DQ6 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command ...
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AC Characteristics Alternate CE# Controlled Erase and Program Operations- S29GL128N, S29GL256N, S29GL512N Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS Address Setup Time to OE# low during T ...
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Characteristics 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a ...
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Erase And Programming Performance Parameter Sector Erase Time S29GL128N Chip Erase Time S29GL256N S29GL512N T otal Write Buffer Programming Time (Note 3) T otal Accelerated Effective Write Buffer Programming Time (Note 3) S29GL128N Chip Program Time S29GL256N S29GL512N Notes: 1. ...
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CellularRAM Type 2 128/64/32 Megabit Burst CellularRAM Features T Single device supports asynchronous, page, and burst operations T VCC Voltages — 1.70V–1.95V Random Access Time: 70ns T Burst Mode Write ...
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DRAM array that contains essential data. T emperature compen- sated refresh (TCR) adjusts the refresh rate to match the device temperature— the refresh rate decreases at lower temperatures to minimize current consump- tion during standby. Deep ...
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Symbol Type 128M: A[ 22:0] Address Inputs: Inputs for addresses during READ and WRITE operations. Addresses are 64M: A[ 21: 0] Input internally latched during READ and WRITE cycles. The address lines are ...
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Table 16. Bus Operations—Asynchronous Mode CLK MODE POWER (Note Read Active Write Active Standby Standby No Operation Idle Configuration Active Register Deep DPD Power-down Notes: 1. CLK may be HIGH or LOW, but must be static during synchronous read, synchronous ...
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CLK MODE POWER (Note Async Read Active Async Write Active Standby Standby No Operation Idle Initial Burst Read Active Initial Burst Write Active Burst Continue Active Burst Suspend Active Configuration Active Register Deep ...
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1 Bus Operating Modes CellularRAM products incorporate a burst mode interface found on Flash products targeting low-power, wireless applications. This bus interface supports asynchro- nous, page mode, and burst mode read ...
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CE# OE# WE# ADDRESS DATA LB#/UB# Figure 24. WRITE Operation (ADV# LOW) Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page mode-capable products, an ...
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CE# OE# WE# ADDRESS DATA LB#/UB# Figure 25. Page Mode READ Operation (ADV# LOW) Burst Mode Operation Burst mode operations enable high-speed synchronous READ and WRITE opera- tions. Burst operations consist of a multi-clock sequence that must be performed in ...
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cause CE# to remain LOW for longer than t the burst restarted with a new CE# LOW/ADV# LOW cycle. CLK Address A[22:0] Valid ADV# CE# OE# WE# WAIT DQ[15:0] LB#/UB# READ Burst Identified ...
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Mixed-Mode Operation The device can support a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for synchronous operation. The asynchronous WRITE operation requires that the clock (CLK) remain static (HIGH or LOW) during the entire ...
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LB#/UB# Operation The LB# enable and UB# enable signals support byte-wide data transfers. During READ operations, the enabled byte(s) are driven onto the DQs. The DQs associ- ated with a disabled byte are ...
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V IH CLK Address A[22:0] Valid ADV LB#/UB High ...
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Partial Array Refresh Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by re- freshing only that part ...
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A[22:0] (except A19) Select Control Register A19 (Note) CRE t VPH ADV# CE# OE# WE# LB#/UB# DQ[15:0] Note: A[19] = LOW to load RCR; A[19] = HIGH to load BCR. Figure 31. Configuration Register WRITE, Asynchronous Mode Followed by READ ...
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CLK Latch Control Register Value A[22:0] OPCODE (except A19 A19 (Note CRE ADV CSP CE# OE WE# ...
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The BCR is accessed using CRE and A[19] HIGH. Table 18. Bus Configuration Register Definition A[22:20] A19 A[18:16] A15 22–20 19 18–16 15 Register Operating Reserved Reserved Select Mode All must be set to "0" Must be set to "0" ...
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4-WORD STARTING BURST BURST WRAP ADDRESS LENGTH BCR[3] WRAP (DECIMAL) LINEAR 0 0-1-2-3 1 1-2-3-0 2 2-3-0-1 3 3-0-1 Yes … 0-1-2-3 1 1-2-3-4 2 ...
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Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive Strength The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. The reduced-strength options are intended for stacked chip (Flash ...
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CLK WAIT DQ[15:0] Note: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 34. WAIT Configuration (BCR[ CLK WAIT WAIT DQ[15: Note: ...
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V IH CLK A[21:0] Valid Address ADV Code A/DQ[15: Code A/DQ[15: Code A/DQ[15: Figure 36. ...
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Table 22. Refresh Configuration Register Mapping A[22:20] A19 A[18:8] 22–20 19 18–8 Register Reserved Reserved Select All must be set to "0" All must be set to "0" RCR[19] Register Select 0 Select ...
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Table 24. 64Mb Address Patterns for PAR (RCR[ RCR[2] RCR[1] RCR[ Table 25. 32Mb ...
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Absolute Maximum Ratings Voltage to Any Ball Except V Relative to V Voltage on V Supply Relative Voltage Supply Relative Storage Temperature (plastic) . ...
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DC Characteristics Table 26. Electrical Characteristics and Operating Conditions Description Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Output High Voltage I OH Output Low Voltage I OL Input Leakage Current Output ...
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Table 27. Temperature Compensated Refresh Specifications and Conditions Description Temperature Compensated Refresh Standby Current Note: I (MAX) values measured with TCR set to 85°C. PAR Table 28. Partial Array Refresh Specifications and Conditions ...
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AC Characteristics Q/2 Input (Note 2) (Note Notes test inputs are driven for a logic 1 and Input timing begins at V Q/2. CC ...
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Table 31. Asynchronous READ Cycle Timing Requirements Parameter Address Access Time ADV# Access Time P age Access Time Address Hold from ADV# HIGH Address Setup to ADV# HIGH LB# / UB# Access Time ...
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Table 32. Burst READ Cycle Timing Requirements Parameter Burst to READ Access Time (Variable Latency) CLK to Output Delay Address Setup to ADV# HIGH Burst OE# LOW to Output Delay CE# HIGH between Subsequent Mixed-Mode Operations CE# LOW to WAIT ...
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Table 33. Asynchronous WRITE Cycle Timing Requirements Parameter Address and ADV# LOW Setup Time Address Hold from ADV# Going HIGH Address Setup to ADV# Going HIGH Address Valid to End of Write LB# ...
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Table 34. Burst WRITE Cycle Timing Requirements (Continued) Parameter Clock Period CE# Setup to CLK Active Edge Hold Time from Active CLK Edge Chip Disable to WAIT High-Z Output CLK Rise or Fall Time Clock to WAIT Valid CLK HIGH ...
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ADV CBPH LB#/UB OE ...
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Table 36. Asynchronous READ Timing Parameters (Continued) 70ns/80 MHz Symbol Min t 1 CEW OHZ t 5 OLZ 134 ...
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VPH V IH ADV CBPH LB#/UB OE# ...
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Table 37. Asynchronous READ Timing Parameters Using ADV# (Continued) 70ns/80 MHz Symbol Min t 10 CVS t 5 AVH t 10 AVS BHZ t 10 BLZ t 5 CBPH t 1 CEW CVS ...
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ADV CBPH ...
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Table 38. Asynchronous READ Timing Parameters—Page Mode Operation (Continued) 70ns/80 MHz Symbol Min t 10 BLZ t 5 CBPH t CEM t 1 CEW OHZ t 5 ...
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CLK VALID ADDRESS ADV CSP V IH CE# V ...
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Table 39. Burst READ Timing Parameters—Single Access, Variable Latency (Continued) 70ns/80 MHz Symbol Min t BOE t 1 CEW t 12.5 CLK t 4 CSP KHKL t KHTL t 2 KOH ...
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CLK Valid Address ADV CSP ...
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Table 40. Burst READ Timing Parameters—4-word Burst 70ns/80 MHz Symbol Min t ABA t ACLK t BOE t 5 CBPH t 1 CEW t 12.5 CLK t 4 CSP KHKL t KHTL t 2 ...
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CLK Valid Address ADV CSP ...
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Table 41. Burst READ Timing Parameters—4-word Burst with LB#/UB# 70ns/80 MHz Symbol Min t ACLK t BOE t 5 CBPH t 1 CEW t 12.5 CLK t 4 CSP KHTL t 3 KHZ t ...
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CLK Valid Address ADV CSP ...
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Table 42. Burst READ Timing Parameters—Burst Suspend (Continued) 70ns/80 MHz Symbol Min CLK CLK ADV ...
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ADV CE LB#/UB OE ...
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Table 44. Asynchronous WRITE Timing Parameters—CE#-Controlled (Continued) 70ns/80 MHz Symbol Min t 1 CEW WHZ WPH t ...
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ADV CE LB#/UB OE ...
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Table 45. Asynchronous WRITE Timing Parameters—LB#/UB#-Controlled (Continued) 70ns/80 MHz Symbol Min t CEM t 1 CEW WHZ ...
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ADV CE LB#/UB OE ...
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Table 46. Asynchronous WRITE Timing Parameters—WE#-Controlled (Continued) 70ns/80 MHz Symbol Min CEM t 1 CEW ...
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ADV CE LB#/UB OE ...
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Table 47. Asynchronous WRITE Timing Parameters Using ADV# 70ns/80 MHz Symbol Min AVH t 10 AVS CEM t 1 CEW ...
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CLK Valid Address ADV ...
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Table 48. Burst WRITE Timing Parameters 70ns/80 MHz Symbol Min t 5 CBPH t 1 CEW t 12.5 CLK t 4 CSP KHKL t KHTL 156 A d ...
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CLK CLK ADV LB#/UB CE ...
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CLK V IH CLK Valid Address ADV ...
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Table 51. READ Timing Parameters—Burst WRITE Followed by Burst READ (Continued) 70ns/80 MHz Symbol Min t 4 CSP KOH t OHZ CLK V ...
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Table 52. WRITE Timing Parameters—Asynchronous WRITE Followed by Burst READ 70ns/80 MHz Symbol Min t 5 AVH AVS CKA t 10 CVS ...
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CLK Valid Valid Address Address ADV ...
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Table 54. Asynchronous WRITE Timing Parameters—ADV# LOW (Continued) 70ns/80 MHz Symbol Min WPH 70ns/80 MHz Symbol Min t ACLK t BOE t 5 CBPH t 1 CEW t 12.5 CLK t 4 ...
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CLK Valid Address ADV CSP ...
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MHz Symbol Min t ACLK t BOE t 5 CBPH t 1 CEW t 12.5 CLK t 4 CSP KHKL t KHTL t 2 KOH OHZ Table 57. Asynchronous ...
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CLK Valid Address ADV CSP ...
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MHz Symbol Min t ACLK t BOE t 5 CBPH t 1 CEW t 12.5 CLK t 4 CSP KHKL t KHTL t 2 KOH OHZ Table 59. Asynchronous ...
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Table 59. Asynchronous WRITE Timing Parameters Using ADV# (Continued) 70ns/80 MHz Symbol Min Valid Address ADV# V ...
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Table 60. WRITE Timing Parameters—ADV# LOW (Continued) 70ns/80 MHz Symbol Min WHZ WPH Table 61. READ Timing Parameters—ADV# LOW 70ns/80 ...
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Valid Address AVS t AVH t VPH ADV CVS V IH LB#/UB ...
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Table 62. WRITE Timing Parameters—Asynchronous WRITE Followed by Asynchronous READ 70ns/80 MHz Symbol Min VPH WHZ WPH Table 63. READ ...
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Asynchronous WRITE Operation The timing parameters provided in must be completed within 4µs. After completing a WRITE operation, the device must either enter standby (by transitioning CE# HIGH), or else perform a second ...
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ADDRESS CE# LB#/UB# WE# DATA Page Mode READ Operation When a CellularRAM device is configured for page mode operation, the address inputs are used to accelerate read accesses and cannot be used by the on-chip circuitry to schedule ...
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CellularRAM-2A 64 Megabit Asynchronous CellularRAM Features T Asynchronous and Page Mode interface T Random Access Time Page Mode Read Access — Sixteen-word page size — Interpage read access ...
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These three refresh mechanisms are accessed through the CR. A[21:0] CE# WE# OE# Control LB# Logic UB# ZZ# Note: Functional block diagrams illustrate simplified device operation. ...
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Symbol Type V Q Supply V Q must be connected to ground Table 66. Bus Operations—Asynchronous Mode Mode Power Standby Standby Read Active > Standby Write Active > Standby Active Standby ...
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Functional Description The 64Mb async/page CellularRAM device is a high-density alternative to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The de- vice contains 67,108,864 bits organized as 4,194,304 addresses by 16 bits. It includes the industry-standard, asynchronous ...
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CE# OE# WE# ADDRESS DATA LB#/UB# Don't Care CE# OE# WE# ADDRESS DATA LB#/UB# Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page mode-capable ...
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Page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. WRITE operations do not include comparable page mode functionality. CE# OE# WE# ADDRESS DATA LB#/UB# LB# / UB# ...
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frequent refresh operations to maintain data integrity as temperatures increase. More frequent refresh is required due to the increased leakage of the DRAM's ca- pacitive storage elements as temperatures rise. A decreased refresh ...
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Page mode control is also embedded into the configuration register. Table 67 is set to 0070h. ADDRESS CE# WE# ZZ# Figure 69. Load Configuration Register Operation Partial Array ...
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Table 67. Configuration Register Bit Mapping A[21:8] 21–8 RESERVED All must be set to "0" CR[7] Page Mode Enable/Disable 0 Page Mode Disabled (default) 1 Page Mode Enabled CR[6] CR[5] Maximum Case Temp. ...
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Absolute Maximum Ratings Voltage to Any Ball Except V Relative to V Voltage on V Supply Relative Voltage Supply Relative Storage Temperature . . . . . . . . . ...
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Characteristics Wireless Temperature (-25°C ≤ ndustrial T emperature (-40°C < T Table 69. Electrical Characteristics and Operating Conditions Description Supply Voltage I/ O Supply Voltage Input High Voltage Input Low ...
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Table 71. Partial Array Refresh Specifications and Conditions Description V Partially Array Refresh Current Note:I (MAX) values measured with TCR set to 85°C. PAR Description Deep Power-down Table 73. Capacitance Specifications and Conditions Description Input Capacitance ...
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Table 75. READ Cycle Timing Requirements Parameter Address Access Time Page Access Time LB# / UB# Access Time LB# / UB# Disable to High-Z Output LB# / UB# Enable to Low-Z Output Chip ...
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Table 76. WRITE Cycle Timing Requirements Parameter Address Setup Time Address Valid to End of Write Byte Select to End of Write CE# HIGH Time During Write Maximum CE# Pulse Width Chip Enable to End of Write Data Hold from ...
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Table 79. Power-up Initialization Timing Parameters Parameter Initialization Period (required before normal operations 1.7V ADDRESS CE# LB#/UB# WE# OE# ZZ# Figure 73. Load Configuration Register Timing ...
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CDZZ t ZZ (MIN) ZZ Figure 74. Deep Power Down Entry/Exit TIming Table 81. Load Configuration Register Timing Requirements t ADDRESS CE# LB#/UB# OE# DATA-OUT Figure 75. Single READ Operation (WE 188 ...
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Symbol BHZ t BLZ ADDRESS A[21:4] ADDRESS A[3:0] t CE# LB#/UB# t BLZ t LZ OE# t OLZ High-Z DATA-OUT Figure 76. Page Mode ...
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ADDRESS CE# LB#/UB# WE# OE# DATA-IN DATA-OUT Symbol CEM 190 ...
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ADDRESS LB#/UB# DATA-IN DATA-OUT Figure 78. Write Timing Parameters (CE# Control) Table 85. Write Timing Parameters (CE# Control) Symbol CEH t CEM ...
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ADDRESS CE# LB#/UB# WE# OE# DATA-IN DATA-OUT Figure 79. WRITE Cycle (LB# / UB# Control) Table 86. Write Timing Parameters (LB# / UB# Control) Symbol CEM t DH 192 ...
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How Extended Timings Impact CellularRAM™ Operation Introduction CellularRAM products use a DRAM technology that periodically requires refresh to ensure against data corruption. CellularRAM devices include on-chip circuitry that performs the required refresh in ...
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Note:Timing constraints when page mode is enabled. Impact on Extended WRITE Operations Modified timings are only required during extended WRITE operations (see 83 below). An extended WRITE operation requires that both the write pulse width (t ) and the data ...
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Revision Summary Revision A0 (December 17, 2004) I nitial release. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, ...