m36p0r9060n0 Numonyx, m36p0r9060n0 Datasheet

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m36p0r9060n0

Manufacturer Part Number
m36p0r9060n0
Description
512 Mbit X16, Multiple Bank, Multi-level, Burst Flash Memory 64 Mbit Burst Psram, 1.8v Supply, Mux I/o, Multi-chip Package
Manufacturer
Numonyx
Datasheet
Feature summary
Flash memory
November 2007
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
64 Mbit (Burst) PSRAM, 1.8V supply, Mux I/O, Multi-Chip Package
Multi-Chip Package
– 1 die of 512 Mbit (32Mb x 16, Multiple
– 1 die of 64 Mbit (4Mb x16) PSRAM
Supply voltage
– V
– V
Electronic signature
– Manufacturer Code: 20h
– Device Code: 8833
ECOPACK® package
Multiplexed Address/Data
Synchronous / Asynchronous Read
– Synchronous Burst Read mode:
– Asynchronous Page Read mode
– Random Access: 96ns
Programming time
– 4.2µs typical Word program time using
Memory organization
– Multiple Bank Memory Array: 64 Mbit
– Four Extended Flash Array (EFA) Blocks of
Dual operations
– program/erase in one Bank while read in
– No delay between read and write
Security
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
Bank, Multi-Level, Burst) Flash memory
108MHz, 66MHz
Buffer Enhanced Factory Program
command
Banks
64 Kbits
others
operations
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory
DDF
PPF
= 9V for fast program
= V
CCP
= V
DDQ
= 1.7 to 1.95V
Rev 0.2
PSRAM
100,000 Program/erase cycles per block
Block locking
– All Blocks locked at power-up
– Any combination of Blocks can be locked
– WP
– Absolute Write Protection with V
Common Flash Interface (CFI)
Multiplexed Address/Data bus
Asynchronous operating modes
– Random Read: 70ns access time
– Asynchronous Write
Synchronous modes
– Synchronous Read: Fixed length (4-, 8-,
– Clock Frequency: 83MHz (max)
– Synchronous Write: continuous burst
Low-power features
– Partial Array Self-Refresh (PASR)
– Deep Power-Down (DPD) mode
– Automatic Temperature-compensated Self-
with zero latency
16-, and 32-Word) or continuous burst
Refresh
F
for Block Lock-Down
M36P0R9060N0
TFBGA107 (ZAN)
FBGA
Preliminary Data
www.numonyx.com
PPF
= V
1/23
SS
1

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m36p0r9060n0 Summary of contents

Page 1

... OTP Cells November 2007 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. M36P0R9060N0 FBGA TFBGA107 (ZAN) ■ 100,000 Program/erase cycles per block ■ ...

Page 2

... PSRAM Configuration Register Enable (CR 2.17 Deep Power-Down input (DPD 2.18 V Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DDF 2.19 V Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CCP 2.20 V Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DDQ 2.21 V Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PPF 2.22 V Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/ M36P0R9060N0 ) . . . . . . . . . . . . . . . . . . . . . 11 ...

Page 3

... M36P0R9060N0 6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3/23 ...

Page 4

... List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 7. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4/23 M36P0R9060N0 ...

Page 5

... M36P0R9060N0 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. TFBGA connections (top view through package Figure 3. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. TFBGA 107 8x11mm - 9x12 active ball array, 0.8mm pitch, package outline . . . . . . . . . . 19 5/23 ...

Page 6

... Summary description 1 Summary description The M36P0R9060N0 combines two memory devices in a Multi-Chip Package: ● 512-Mbit Multiple Bank Flash memory (the M58PR512JN) ● 64-Mbit PSRAM (the M69KM096AA). The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58PRxxxJN and M69KM096AA datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed ...

Page 7

... M36P0R9060N0 Table 1. Signal names (1) A16-A24 ADQ0-ADQ15 V DDQ V PPF V DDF V CCP WAIT NC DU Flash Memory DPD F PSRAM A22-A24 are Address Inputs for the Flash memory component only. Address Inputs ...

Page 8

... ADQ8 ADQ2 ADQ10 ADQ0 ADQ1 ADQ3 ADQ9 ADQ11 DDF DDQ M36P0R9060N0 CCP V SS DPD DDF A21 A22 A20 ...

Page 9

... M36P0R9060N0 2 Signal descriptions See Figure 1., Logic diagram connected to this device. 2.1 Address Inputs (ADQ0-ADQ15 and A16-A24) Addresses A0-A21 are common inputs for the Flash memory and PSRAM components. Addresses A22 and A24 are inputs for the Flash memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations ...

Page 10

... F , Lock-Down is enabled and the protection status of the Locked Refer to the M58PRxxxJN datasheet, for the DD2 , the device is in normal operation. Exiting Reset mode the IH M36P0R9060N0 , and Reset is High the Flash memory are deselected, the , Lock-Down is disabled IH , the IH , the IL ...

Page 11

... M36P0R9060N0 2.11 PSRAM Chip Enable input (E The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted (V ), the device is disabled, and goes automatically in low-power Standby mode or Deep IH Power-down mode, according to the RCR (Refresh Configuration Register) setting. 2.12 PSRAM Write Enable (W Write Enable, W ...

Page 12

... Program/Erase algorithm is completed. 12/ CCP DDQ gives an absolute protection against Program or Erase, PPLK enables these functions (see the M58PRxxxJN datasheet for the relevant it acts as a power supply pin. In this condition V PPH M36P0R9060N0 ) V is seen as a control input. In this PPF PPF must be ...

Page 13

... M36P0R9060N0 2.22 V Ground the common ground reference for all voltage measurements in the Flashmemory SS (core and I/O Buffers) and PSRAM chips. It must be connected to the system ground. Note: Each Flash memory device in a system should have their supply voltage (V the program supply voltage V (high frequency, inherently low inductance capacitors should be as close as possible to the package) ...

Page 14

... Figure 3. Functional block diagram A22-A24 A16-A21 14/ DDF PPF 512 Mbit RP F Flash Memory CCP Mbit G P PSRAM M36P0R9060N0 for the Flash memory F DPD F WAIT ADQ0-ADQ15 DDQ Ai13419 ...

Page 15

... M36P0R9060N0 Table 2. Main operating modes (2) Operation Bus Read Bus Write Address Latch Output Disable Standby Reset X X Deep Power-Down Read Write Flash memory must be disabled Read CR (CR controlled method) ...

Page 16

... DDF V PSRAM Supply Voltage CCP V Input/Output Supply Voltage DDQ V Flash Memory Program Voltage PPF I Output Short Circuit Current O t Time for V VPPH 16/23 Parameter at V PPF PPH M36P0R9060N0 Value Unit Min Max –30 85 °C –30 85 °C –55 125 °C –0.2 2.45 V –1.0 3.0 V –0.2 2 ...

Page 17

... M36P0R9060N0 5 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4., Operating and AC measurement operating conditions in their circuit match the operating conditions when relying on the quoted parameters ...

Page 18

... Sampled only, not 100% tested. Please refer to the M58PRxxxJN and M69KM096AA datasheets for further DC and AC characteristics values and illustrations. 18/23 DEVICE UNDER TEST CCP (1) Parameter Test Condition OUT M36P0R9060N0 V /2 DDQ R OUT C L AI13228 Min Max Unit – 14 – ...

Page 19

... M36P0R9060N0 6 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ...

Page 20

... Stacked TFBGA107 8x11mm - 9x12 active ball array, 0.8mm pitch, package data Symbol ddd 20/23 millimeters Typ Min Max 1.20 0.20 0.85 0.35 0.30 0.40 8.00 7.90 8.10 6.40 0.10 11.00 10.90 11.10 8.80 0.80 0.80 1.10 0.40 M36P0R9060N0 inches Typ Min Max 0.047 0.008 0.033 0.014 0.012 0.016 0.315 0.311 0.319 0.252 0.004 0.433 0.429 0.437 0.346 0.031 0.031 0.043 0.016 ...

Page 21

... M36P0R9060N0 7 Part numbering Table 7. Ordering information scheme Example: Device Type M36 = Multi-Chip Package (Flash + PSRAM) Flash 1 Architecture P = Multi-Level, Multiple Bank, Large Buffer Flash 2 Architecture Die Operating Voltage DDF CCP Flash 1 Density 9 = 512 Mbits Flash 2 Density Die RAM 1 Density ...

Page 22

... Revision history 8 Revision history Table 8. Document revision history Date 21-Jul-2006 30-Nov-2007 22/23 Revision 0.1 Initial release. 0.2 Applied Numonyx branding. M36P0R9060N0 Changes ...

Page 23

... M36P0R9060N0 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ...

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