mh2080 Music Semiconductors, Inc., mh2080 Datasheet - Page 12
mh2080
Manufacturer Part Number
mh2080
Description
Hla Packaged Asynchronous Data Recognition And Recall Processor
Manufacturer
Music Semiconductors, Inc.
Datasheet
1.MH2080.pdf
(34 pages)
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PA:AA Bus and the Status Register
The Status Register bits SR15-0 reflect the PA:AA bus
under all conditions. The Status Register flags /MF, /MM,
and /FF represent the local conditions within the device,
and are not conditioned by the /MI and /FI inputs.
After a Comparison cycle, Write at Next Free address, or
access to the Highest-Priority Matching device, a Status
Register Read cycle is executed in the same device as the
12
active PA:AA bus. In the case of a random access Read or
Write cycle, the Status register of any selected device can
be accessed by a Read Status Register cycle. The system
designer must ensure that a Status Register Read cycle
after a random Read or Write cycle is into a single device
using Chip Select /CS1, /CS2, or the Device Select
register to prevent bus contention on the DQ31-0 bus.
Rev. 1.1a
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