am41dl3208gt85it Meet Spansion Inc., am41dl3208gt85it Datasheet - Page 17

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am41dl3208gt85it

Manufacturer Part Number
am41dl3208gt85it
Description
32 Mbit 4 M ? 8-bit/2 M ? 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 8 Mbit 1 M ? 8-bit/512 K ? 16-bit Static Ram Preliminary
Manufacturer
Meet Spansion Inc.
Datasheet
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE#f and RESET# pins are both held at V
(Note that this is a more restricted voltage range than
V
within V
mode, but the standby current will be greater. The de-
vice requires standard access time (t
access when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of
the CE#f, WE#, and OE# control signals. Standard ad-
d r e ss a cce s s t im in g s p ro v id e n e w d a t a w h e n
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
the device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was
16
CC3
CC4
IH
.) If CE#f and RESET# are held at V
in the DC Characteristics table represents the
in the DC Characteristics table represents the
CC
± 0.3 V, the device will be in the standby
CE
P R E L I M I N A R Y
CC
IH
) for read
, but not
± 0.3 V.
ACC
Am41DL3208G
RP
+
,
interrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
vice draws CMOS standby current (I
held at V
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
system can thus mon itor RY/BY# to de term ine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is
completed within a time of t
ded Algorithms). The system can read data t
the RESET# pin returns to V
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 15 for the timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high
impedance state.
Bank 1
Bank 2
Bank 3
Bank 4
Bank
READY
IL
Table 5. Device Bank Division
but not within V
Megabits
(during Embedded Algorithms). The
12 Mb
12 Mb
4 Mb
4 Mb
Twenty-four 64 Kbyte/32 Kword
Twenty-four 64 Kbyte/32 Kword
SS
IH
Seven 64 Kbyte/32 Kword
READY
Eight 64 Kbyte/32 Kword
IH
, output from the device is
Eight 8 Kbyte/4 Kword,
± 0.3 V, the standby cur-
.
Sector Sizes
(not during Embed-
February 13, 2002
SS
CC4
± 0.3 V, the de-
). If RESET# is
RH
after

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