am41dl3208gt85it Meet Spansion Inc., am41dl3208gt85it Datasheet - Page 29

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am41dl3208gt85it

Manufacturer Part Number
am41dl3208gt85it
Description
32 Mbit 4 M ? 8-bit/2 M ? 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 8 Mbit 1 M ? 8-bit/512 K ? 16-bit Static Ram Preliminary
Manufacturer
Meet Spansion Inc.
Datasheet
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device
operations. Tables 15 and 16 define the valid register
command sequences. Writing incorrect address and
data values or writing them in the improper se-
quence resets the device to reading array data.
All addresses are latched on the falling edge of WE#
or CE#f, whichever happens later. All data is latched
on the rising edge of WE# or CE#f, whichever hap-
pens first. Refer to the AC Characteristics section for
timing diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
t he co rresp on din g ba n k e nt ers th e era se-su s-
pend-read mode, after which the system can read
data from any non-erase-suspended sector within the
same bank. After completing a programming operation
in the Erase Suspend mode, the system may once
again read array data with the same exception. See
the Erase Suspend/Erase Resume Commands sec-
tion for more information.
The system must issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See the
next section, Reset Command, for more information.
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Flash Read-Only Operations table provides the
read parameters, and Figure 14 shows the timing
diagram.
Reset Command
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the bank to which the sys-
tem was writing to reading array data. Once erasure
begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the bank to
28
P R E L I M I N A R Y
Am41DL3208G
which the system was writing to reading array data. If
the program command sequence is written to a bank
that is in the Erase Suspend mode, writing the reset
co m m a nd r et u rn s t h a t ba n k t o t he e r as e -su s-
p e n d - re a d m o d e . O n c e p r o g r a m m in g b e g i n s,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to reading array data. If a
bank entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns
that bank to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to read-
ing array data (or erase-suspend-read mode if that
bank was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
Tables 15 and 16 show the address and data require-
ments. The autoselect command sequence may be
written to an address within a bank that is either in the
read or erase-suspend-read mode. The autoselect
command may not be written while the device is ac-
tively programming or erasing in the other bank.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the au-
to s e le c t co m m a n d . T h e b a n k t h e n e n t e r s t h e
autoselect mode. The system may read at any ad-
dress within the same bank any number of times
witho ut initiating ano ther a utosele ct co mm and
sequence:
I A read cycle at address (BA)XX00h (where BA is
I A read cycle at address (BA)XX01h in word mode
I A read cycle to an address containing a sector ad-
The system must write the reset command to return to
reading array data (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
the bank address) returns the manufacturer code.
(or (BA)XX02h in byte mode) returns the device
code.
dress (SA) within the same bank, and the address
02h on A7–A0 in word mode (or the address 04h on
A6–A-1 in byte mode) returns 01h if the sector is
protected, or 00h if it is unprotected. (Refer to Ta-
bles 6–8 for valid sector addresses).
February 13, 2002

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