am41dl3208gt85it Meet Spansion Inc., am41dl3208gt85it Datasheet - Page 4

• Manufacturer Part Number: am41dl3208gt85it
• Description: 32 Mbit 4 M ? 8-bit/2 M ? 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 8 Mbit 1 M ? 8-bit/512 K ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Common Flash Memory Interface (CFI) . . . . . . . 25
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 28
February 13, 2002
Special Handling Instructions for FBGA Package .................... 7
Word/Byte Configuration ........................................................ 15
Requirements for Reading Array Data ................................... 15
Writing Commands/Command Sequences ............................ 15
Simultaneous Read/Write Operations with Zero Latency ....... 15
Standby Mode ........................................................................ 16
Automatic Sleep Mode ........................................................... 16
RESET#: Hardware Reset Pin ............................................... 16
Output Disable Mode .............................................................. 16
Autoselect Mode ..................................................................... 21
Sector/Sector Block Protection and Unprotection .................. 21
Write Protect (WP#) ................................................................ 21
Temporary Sector/Sector Block Unprotect ............................. 22
SecSi (Secured Silicon) Sector Flash Memory Region .......... 24
Hardware Data Protection ...................................................... 24
Reading Array Data ................................................................ 28
Table 1. Device Bus Operations—Flash Word Mode, CIOf = V
SRAM Word Mode, CIOs = V
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
SRAM Byte Mode, CIOs = V
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
SRAM Word Mode, CIOs = V
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
Byte Mode, CIOs = V
Accelerated Program Operation .......................................... 15
Autoselect Functions ........................................................... 15
Table 5. Device Bank Division ........................................................16
Table 6. Top Boot Sector Addresses .............................................17
Table 8. Bottom Boot Sector Addresses .........................................19
Table 10. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................21
Figure 1. Temporary Sector Unprotect Operation........................... 22
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algo-
rithms .............................................................................................. 23
Factory Locked: SecSi Sector Programmed and Protected At
the Factory .......................................................................... 24
Customer Lockable: SecSi Sector NOT Programmed or Pro-
tected At the Factory ........................................................... 24
Low V
Write Pulse “Glitch” Protection ............................................ 24
Logical Inhibit ...................................................................... 24
Power-Up Write Inhibit ......................................................... 25
Table 11. CFI Query Identification String ........................................ 25
System Interface String................................................................... 26
Table 13. Device Geometry Definition ............................................ 26
Table 14. Primary Vendor-Specific Extended Query ...................... 27
Top Boot SecSi Sector Addresses ............................................. 18
Bottom Boot SecSi Sector Addresses ........................................ 20
CC
Write Inhibit ........................................................... 24
SS
..................................................................14
SS
CC
CC
..................................................... 11
......................................................12
.....................................................13
P R E L I M I N A R Y
IL
; SRAM
SS
IH
IH
Am41DL3208G
;
;
;
Write Operation Status . . . . . . . . . . . . . . . . . . . . 34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 38
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 38
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
SRAM DC and Operating Characteristics . . . . . 40
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Key To Switching Waveforms . . . . . . . . . . . . . . . 42
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43
Reset Command ..................................................................... 28
Autoselect Command Sequence ............................................ 28
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 29
Byte/Word Program Command Sequence ............................. 29
Chip Erase Command Sequence ........................................... 30
Sector Erase Command Sequence ........................................ 30
Erase Suspend/Erase Resume Commands ........................... 31
DQ7: Data# Polling ................................................................. 34
RY/BY#: Ready/Busy# ............................................................ 35
DQ6: Toggle Bit I .................................................................... 35
DQ2: Toggle Bit II ................................................................... 36
Reading Toggle Bits DQ6/DQ2 ............................................... 36
DQ5: Exceeded Timing Limits ................................................ 36
DQ3: Sector Erase Timer ....................................................... 36
CMOS Compatible .................................................................. 39
Zero-Power Flash ................................................................. 41
SRAM CE#s Timing ................................................................ 43
Flash Read-Only Operations ................................................. 44
Hardware Reset (RESET#) .................................................... 45
Flash Word/Byte Configuration (CIOf) .................................... 46
Flash Erase and Program Operations .................................... 47
Unlock Bypass Command Sequence .................................. 29
Figure 3. Program Operation ......................................................... 30
Figure 4. Erase Operation.............................................................. 31
Table 15. Command Definitions (Flash Word Mode) ...................... 32
Table 16. Command Definitions (Flash Byte Mode) ....................... 33
Figure 5. Data# Polling Algorithm .................................................. 34
Figure 6. Toggle Bit Algorithm........................................................ 35
Table 17. Write Operation Status ................................................... 37
Industrial (I) Devices ............................................................ 38
V
Figure 9. I
Currents) ........................................................................................ 41
Figure 10. Typical I
Figure 11. Test Setup.................................................................... 42
Table 18. Test Specifications ......................................................... 42
Figure 12. Input Waveforms and Measurement Levels ................. 42
Figure 13. Timing Diagram for Alternating Between SRAM to Flash ..
43
Figure 14. Read Operation Timings ............................................... 44
Figure 15. Reset Timings ............................................................... 45
Figure 16. CIOf Timings for Read Operations................................ 46
Figure 17. CIOf Timings for Write Operations................................ 46
Figure 18. Program Operation Timings.......................................... 48
Figure 19. Accelerated Program Timing Diagram.......................... 48
Figure 20. Chip/Sector Erase Operation Timings .......................... 49
Figure 21. Back-to-back Read/Write Cycle Timings ...................... 50
Figure 22. Data# Polling Timings (During Embedded Algorithms). 50
Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 51
Figure 24. DQ2 vs. DQ6................................................................. 51
CC
f/V
CC
s Supply Voltage ................................................... 38
CC1
Current vs. Time (Showing Active and Automatic Sleep
CC1
vs. Frequency ............................................ 41
3