am41dl16x4d Meet Spansion Inc., am41dl16x4d Datasheet

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am41dl16x4d

Manufacturer Part Number
am41dl16x4d
Description
Stacked Multi-chip Package Mcp Flash Memory And Sram Am29dl16xd 16 Megabit 2 M X 8-bit/1 M X 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 4 Mbit 512 K X 8-bit/256 K X 16-bit Static Ram
Manufacturer
Meet Spansion Inc.
Datasheet
Am41DL16x4D
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 25562 Revision A
Amendment 0 Issue Date October 24, 2001

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am41dl16x4d Summary of contents

Page 1

... Am41DL16x4D Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu ...

Page 2

... PRELIMINARY Am41DL16x4D Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL16xD 16 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High performance — ...

Page 3

... The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode system can also place the de vice into the standby mode. Power consumption is greatly re- duced in both modes. Am41DL16x4D ...

Page 4

... Flash Word/Byte Configuration (CIOf) .................................... 44 Figure 16. CIOf Timings for Read Operations................................ 44 Figure 17. CIOf Timings for Write Operations................................ 44 Flash Erase and Program Operations .................................... 45 Figure 18. Program Operation Timings.......................................... 46 Figure 19. Accelerated Program Timing Diagram.......................... 46 Figure 20. Chip/Sector Erase Operation Timings .......................... 47 Figure 21. Back-to-back Read/Write Cycle Timings ...................... 48 Am41DL16x4D vs. Frequency ............................................ 39 3 ...

Page 5

... Flash Erase And Programming Performance Flash Latchup Characteristics Package Pin Capacitance . . . . . . . . . . . . . . . . . . 59 FLASH Data Retention . . . . . . . . . . . . . . . . . . . . . 59 SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 60 Figure 33. CE1#s Controlled Data Retention Mode....................... 60 Figure 34. CE2s Controlled Data Retention Mode......................... 60 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 61 FLA069—69-Ball Fine-Pitch Grid Array ............... 61 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 62 Revision A (October 24, 2001) ............................................... 62 Am41DL16x4D . 59 ...

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... CIOs Am41DL16x4D Flash Memory RY/BY# 16 Mbit Flash Memory DQ0 to DQ15/A– CCQ SS SSQ 4 Mbit DQ0 to DQ15/A–1 Static RAM Am41DL16x4D SRAM DQ0 to DQ15/A–1 5 ...

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... V SS A19–A0 RY/BY# A19–A0 RESET# STATE CONTROL WE# & CE# COMMAND CIOf REGISTER WP#/ACC DQ15–DQ0 A19– Upper Bank Address Upper Bank X-Decoder Status Control X-Decoder Lower Bank Lower Bank Address Am41DL16x4D OE# CIOf DQ15–DQ0 ...

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... Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150 C for prolonged periods of time. Am41DL16x4D Flash only A10 NC SRAM only Shared C9 A15 D9 NC ...

Page 9

... SRAM Power Supply Device Ground (Common Pin Not Connected Internally LOGIC SYMBOL 18 A0–A17 A–1, A18–A19 SA CE#f CE1#s CE2s OE# WE# WP#/ACC RESET# UB#s LB#s CIOf CIOs Am41DL16x4D DQ15–DQ0 RY/BY# ...

Page 10

... Package Marking ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- M410000000 leased combinations. M410000001 M410000002 M410000003 M410000004 M410000005 M410000006 M410000007 M410000008 M410000009 M41000000A M41000000B M41000000C M41000000D M41000000E M41000000F Am41DL16x4D Valid Combinations 9 ...

Page 11

... chine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the re- sulting output. The following subsections describe each of these operations in further detail. Am41DL16x4D ...

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... Don’t Care SRAM Address Address In Data In and CE2s = V at the same time. IH the boot sectors protection will be removed. IH Am41DL16x4D ; SRAM Word Mode, CIOs = WP#/ACC DQ7– DQ15– (Note 4) DQ0 X H L/H D OUT ...

Page 13

... 9.0 ± 0 Don’t Care SRAM Address Address In Data In and CE2s = V at the same time. IH the boot sectors protection will be removed. IH Am41DL16x4D ; SRAM Byte Mode, CIOs = UB#s WP#/ACC DQ7– RESET# (Note 3) (Note 4) DQ0 X H L/H ...

Page 14

... 9.0 ± 0 Don’t Care SRAM Address Address In (for Flash Byte Mode, DQ15 = A-1 and CE2s = V at the same time. IH the boot sectors protection will be removed. IH Am41DL16x4D ; SRAM Word Mode, CIOs = UB#s WP#/ACC DQ7– RESET# (Note 4) DQ0 X H ...

Page 15

... Don’t Care SRAM Address Address In (for Flash Byte Mode, DQ15 = A-1 and CE2s = V at the same time. IH the boot sectors protection will be removed. IH Am41DL16x4D ; SRAM Byte Mode, CIOs = UB#s WP#/ACC DQ7– RESET# (Note 3) (Note 4) DQ0 ...

Page 16

... Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 represent the current specifications for read-while-pro- gram and read-while-erase, respectively. Am41DL16x4D on this pin, the device auto- HH for operations other than accelerated pro- and I in the DC Characteristics table ...

Page 17

... Mbit Eight 8 Kbyte/4 Kword, 14 Mbit three 64 Kbyte/32 Kword Eight 8 Kbyte/4 Kword, 12 Mbit seven 64 Kbyte/32 Kword Eight 8 Kbyte/4 Kword, 8 Mbit fifteen 64 Kbyte/32 Kword Am41DL16x4D ± 0.3 V, the de RESET# is CC4 ± 0.3 V, the standby cur- SS (during Embedded Algorithms). The (not during Embed- READY after RH ...

Page 18

... A19:A0 in word mode (CIOf=V IL SecSi Sector Addresses for Top Boot Devices Sector Address A19–A12 11111XXX Am41DL16x4D (x8) (x16) Address Range 00000h–07FFFh 08000h–0FFFFh 10000h–17FFFh 18000h–1FFFFh 20000h–27FFFh 28000h–2FFFFh 30000h–37FFFh 38000h–3FFFFh 40000h–47FFFh 48000h– ...

Page 19

... A19:A0 in word mode (BYTE#= and A19 for Am29DL164DB. SecSi Addresses for Bottom Boot Devices Sector Address A19–A12 00000XXX Am41DL16x4D (x8) (x16) Address Range 00000h-00FFFh 01000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-04FFFh 05000h-05FFFh 06000h-06FFFh 07000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh ...

Page 20

... Write Protect (WP#) The Write Protect function provides a hardware method of protecting certain boot sectors without using V . This function is one of two provided by the ID WP#/ACC pin. Am41DL16x4D A19–A12 Sector / Sector Block Size 11111XXX 64 Kbytes 11110XXX, 11101XXX, 192 (3x64) Kbytes ...

Page 21

... Figure 25 shows the timing diagrams, for this feature. Notes: 1. All protected sectors unprotected (If WP#/ACC = V outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation Am41DL16x4D is ID START RESET (Note 1) Perform Erase or ...

Page 22

... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Unprotect Algorithm Am41DL16x4D START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? Yes ...

Page 23

... V and power-down transitions, or from system noise. Low V Write Inhibit CC When V is less than V CC cept any write cycles. This protects data during V power-up and power-down. The command register Am41DL16x4D This IH ID power- the device does not ac- LKO CC ...

Page 24

... Alternatively, contact an AMD representative for copies of these documents. Description Query Unique ASCII string “QRY” Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Am41DL16x4D 23 ...

Page 25

... Max. number of byte in multi-byte write = 2 (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information Am41DL16x4D N µs N µ s (00h = not supported ...

Page 26

... Page Mode Type 00 = Not Supported Word Page Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot Device Am41DL16x4D 25 ...

Page 27

... A7–A0 in word mode (or the address 04h on A6–A-1 in byte mode) returns 01h if the sector is protected, or 00h unprotected. (Refer to Ta- bles 6–7 for valid sector addresses). The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend). Am41DL16x4D ...

Page 28

... Figure 3 illustrates the algorithm for the program oper- a tio Fla Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams. Am41DL16x4D any operation HH 27 ...

Page 29

... Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de- termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Am41DL16x4D ...

Page 30

... Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No Data = FFh? Erasure Completed Notes: 1. See Table 16 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 4. Erase Operation Am41DL16x4D START Embedded Erase algorithm in progress Yes 29 ...

Page 31

... Suspend mode, and requires the bank address. 15. Command is valid when device is ready to read array data or when device is in autoselect mode. Table 17. Autoselect Device IDs (Word Mode) Device Am29DL161D Am29DL162D Am29DL163D Am29DL164D T = Top Boot Sector Bottom Boot Sector Am41DL16x4D Fourth Fifth Sixth Data Addr Data Addr 0001 0081/0001 ...

Page 32

... Command is valid when device is ready to read array data or when device is in autoselect mode. Table 19. Autoselect Device IDs (Byte Mode) Device Am29DL161D Am29DL162D Am29DL163D Am29DL164D T = Top Boot Sector Bottom Boot Sector Am41DL16x4D Fourth Fifth Sixth Data Addr Data Addr Data see Table 19 ...

Page 33

... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm Am41DL16x4D Yes No Yes Yes No ...

Page 34

... Reset Command Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 6. Toggle Bit Algorithm Am41DL16x4D No Yes Yes No Yes ...

Page 35

... DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 20 shows the status of DQ3 relative to the other status bits. Am41DL16x4D ...

Page 36

... The device outputs array data if the system addresses a non-busy bank Table 20. Write Operation Status DQ7 DQ5 DQ6 (Note 2) (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data Data DQ7# Toggle Am41DL16x4D DQ2 DQ3 RY/BY# (Note 2) 0 N/A No toggle Toggle 0 0 N/A Toggle 1 Data Data ...

Page 37

... V f/V s for standard voltage range . . 2 3 Operating ranges define those limits between which the func- tionality of the device is guaranteed –2 +2 +0.5 V 2.0 V Figure 8. Maximum Positive Am41DL16x4D ) . . . . . . . . .–40°C to +85° Overshoot Waveform ...

Page 38

... V s – 0.2V, CE2s – 0.2V CC CE2s 0. 4.0 mA min I = –2.0 mA min I = –100 µ min Am41DL16x4D Min Typ Max Unit 1.0 µA 35 µA 1.0 µA 35 µ 0.2 5 µA 0.2 5 µA 0.2 5 µ ...

Page 39

... –1 CE1#s V – 0.2 V, CE2 V – 0.2 V (CE1#s controlled CE2 0.2 V (CE2s controlled), CIOs = Other input = Am41DL16x4D Min Typ Max Unit 2.3 2 ns. Typical sleep mode current is ACC Min Typ Max Unit –1.0 1.0 µA –1.0 1.0 µ ...

Page 40

... Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note 1500 2000 2500 Time Frequency in MHz Figure 10. Typical I vs. Frequency CC1 Am41DL16x4D 3000 3500 4000 3 ...

Page 41

... Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am41DL16x4D 70 Unit 1 TTL gate 0.0–3 ...

Page 42

... AC CHARACTERISTICS SRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 13. Timing Diagram for Alternating Between Test Setup — t CCR t CCR SRAM to Flash Am41DL16x4D All Speed Options Unit Min CCR t CCR 41 ...

Page 43

... Test Setup CE# Read Toggle and Data# Polling t RC Addresses Stable t ACC OEH t CE HIGH Z Figure 14. Read Operation Timings Am41DL16x4D Speed Options 70 85 Min 70 85 Max Max 70 85 Max 30 35 Max 16 Max 16 Min 0 Min 0 ...

Page 44

... CE#f, OE# RESET Description Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 15. Reset Timings Am41DL16x4D All Speed Options Max 20 Max 500 Min 500 Min 50 Min 20 Min Unit ...

Page 45

... Data Output (DQ7–DQ0) Address DQ15 Input Output t FHQV The falling edge of the last WE# signal t SET ( HOLD AH and t specifications Am41DL16x4D Speed Options 70 85 Unit Data Output (DQ7–DQ0) Address Input Data Output (DQ14–DQ0) ...

Page 46

... Program/Erase Valid to RY/BY# Delay BUSY Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information CE#f low during toggle bit Read Toggle and Data# Polling Am41DL16x4D Speed Options Unit Min 70 85 Min ...

Page 47

... WPH A0h t BUSY is the true data at the program address. OUT Figure 18. Program Operation Timings Am41DL16x4D Read Status Data (last two cycles WHWH1 Status D OUT VHH ...

Page 48

... These waveforms are for the word mode. Figure 20. Chip/Sector Erase Operation Timings SADD 555h for chip erase WPH t DH 30h 10 for Chip Erase t BUSY Am41DL16x4D Read Status Data WHWH2 In Complete Progress ...

Page 49

... OEH GHWL Valid Out t SR/W Read Cycle Complement Complement Status Data Status Data Am41DL16x4D Valid PA Valid PA t CPH t CP Valid Valid In In CE#f Controlled Write Cycles VA High Z Valid Data True High Z True Valid Data ...

Page 50

... AHT AS t AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 24. DQ2 vs. DQ6 Am41DL16x4D Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read 49 ...

Page 51

... VIDR CE#f WE# RY/BY# Figure 25. Temporary Sector/Sector Block Unprotect Min Min Min Min Program or Erase Command Sequence t RSP Timing Diagram Am41DL16x4D All Speed Options Unit 500 ns 250 VIDR ...

Page 52

... For sector protect For sector unprotect SADD = Sector Address Figure 26. Sector/Sector Block Protect and Unprotect Valid* Valid* Verify 60h 40h Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect Timing Diagram Am41DL16x4D Valid* Status 51 ...

Page 53

... See the “Flash Erase And Programming Performance” section for more information Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Am41DL16x4D Speed Options 70 85 Unit ...

Page 54

... SADD for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Am41DL16x4D PA DQ7# D OUT 53 ...

Page 55

... Min Max Max Max Max Min Min Min Min Max Min Max Min Max Min UB#s and/or LB Am41DL16x4D Speed Options Unit ...

Page 56

... At any given temperature and voltage condition, t interconnection CO1 t CO2 OLZ t BLZ t LZ Data Valid Figure 29. SRAM Read Cycle (Max.) is less than t (Min.) both for a given device and from device to device HZ LZ Am41DL16x4D BHZ t OHZ 55 ...

Page 57

... (See Note (See Note 4) High applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am41DL16x4D Speed Options ...

Page 58

... (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am41DL16x4D t (See Note Data Valid High-Z is measured from the beginning of write ...

Page 59

... AS t (See Note 4) WP (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am41DL16x4D t (See Note Data Valid High-Z is measured from the beginning of write ...

Page 60

... V, one pin at a time. CC Test Setup OUT Test Conditions Am41DL16x4D Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec µs µs µs Excludes system level overhead (Note 5) sec , 1,000,000 cycles. Additionally, CC Min Max – ...

Page 61

... V (Note 3.0 V, CE1#s V – 0 (Note 1) See data retention waveforms 0.2 V (CE2s controlled), CIOs = V Data Retention Mode t SDR CE1 0.2 V, CE2s V CC Data Retention Mode t SDR CE2s £ 0.2 V Am41DL16x4D Min Typ Max Unit 1.5 3.3 1.0 10 µA (Note RDR - 0 ...

Page 62

... FLA069—69-Ball Fine-Pitch Grid Array 0.15 C (2x) 8.00 BSC B 0.97 1.40 (max) 1.07 0.20 (min) 0.40 7.20 BSC 0. 11.00 BSC Pin A1 DATUM A Corner Index Mark 7.20 BSC 0.80 0. 0.25 (69x) 0.35 0. 0.08 Am41DL16x4D A DATUM B 0.15 C (2x ...

Page 63

... AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies Am41DL16x4D 62 ...

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