at52br1664at ATMEL Corporation, at52br1664at Datasheet

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at52br1664at

Manufacturer Part Number
at52br1664at
Description
16-megabit Flash 4-megabit Sram Stack Memory
Manufacturer
ATMEL Corporation
Datasheet

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Features
Flash
SRAM
Device Number
AT52BR1664A(T)
16-Mbit (x16) Flash and 4-megabit SRAM
2.7V to 3.3V Operating Voltage
Low Operating Power
Industrial Temperature Range
2.7V to 3.3V Read/Write
Access Time – 70 ns, 90 ns
Sector Erase Architecture
Fast Word Program Time – 12 µs
Suspend/Resume Feature for Erase and Program
Low-power Operation
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
VPP Pin for Write Protection and Accelerated Program/Erase Operations
RESET Input for Device Initialization
Sector Lockdown Support
Top/Bottom Boot Block Configuration
128-bit Protection Register
Minimum 100,000 Erase Cycles
4-megabit (256K x 16)
2.7V to 3.3V V
70 ns Access Time
Fully Static Operation and Tri-state Output
1.2V (Min) Data Retention
– 40 mA Operating Current (Maximum)
– 35 µA Standby Current (Maximum)
– Thirty-one 32K Word (64K Byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout
– Supports Reading and Programming from Any Sector by Suspending Erase of a
– Supports Reading Any Word by Suspending Programming of Any Other Word
– 12 mA Active
– 13 µA Standby
Different Sector
CC
Operating Voltage
Flash Configuration
16M (1M x 16)
SRAM Configuration
4M (256K x 16)
16-megabit
Flash +
4-megabit
SRAM Stack
Memory
AT52BR1664A
AT52BR1664AT
Rev. 3361C–STKD–1/04
1

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at52br1664at Summary of contents

Page 1

... V Operating Voltage CC • Access Time • Fully Static Operation and Tri-state Output • 1.2V (Min) Data Retention Device Number Flash Configuration AT52BR1664A(T) SRAM Configuration 4M (256K x 16) 16M (1M x 16) 16-megabit Flash + 4-megabit SRAM Stack Memory AT52BR1664A AT52BR1664AT Rev. 3361C–STKD–1/04 1 ...

Page 2

CBGA Top View Pin Pin Name Configurations A0 - A17 A18 - A19 CE OE/SOE WE/SWE VCC VPP I/O0-I/O15 SCS1, SCS2 RDY/BUSY SVCC GND/SGND SUB SLB NC RESET AT52BR1664A( ...

Page 3

Description The AT52BR1664A(T) combines a single plane 16-Mbit Flash and a 4-megabit SRAM in a stacked 66-ball CBGA package. Both devices operate at 2.7V to 3.3 in the industrial temperature range. Block Diagram Absolute Maximum Ratings Temperature under Bias.................................. -40° ...

Page 4

Flash Memory Block Diagram OUTPUT BUFFER INPUT A0 - A19 BUFFER ADDRESS LATCH Y-DECODER X-DECODER AT52BR1664A(T) 4 I/O0 - I/O15 INPUT BUFFER IDENTIFIER REGISTER STATUS REGISTER COMMAND REGISTER DATA COMPARATOR WRITE STATE MACHINE Y-GATING MAIN MEMORY ...

Page 5

Flash The 16-Mbit Flash is organized as 1,048,576 words of 16 bits each. The x16 data appears on I/O0 - I/O15. The memory is divided into 39 sectors for erase operations. The device has CE Description and OE control ...

Page 6

Device READ: The Flash is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the out- Operation puts. The outputs ...

Page 7

Any commands written to the chip during the embedded programming cycle will be ignored hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0” cannot be programmed ...

Page 8

TOGGLE BIT: In addition to Data Polling the device provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the memory will result in I/O6 ...

Page 9

SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is through reset or power-up cycles. After power-up or reset, the content of a sector that is locked down can be erased and reprogrammed. ERASE SUSPEND/ERASE ...

Page 10

RDY/BUSY: For the 16-Mbit Flash, an open-drain READY/BUSY output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the ...

Page 11

Figure 1. Data Polling Algorithm (Configuration Register = 00) START Read I/O7 - I/O0 Addr = VA YES I/O7 = Data I/O3, I/ YES Read I/O7 - I/O0 Addr = VA I/O7 = Data? NO Program/Erase ...

Page 12

Figure 3. Toggle Bit Algorithm (Configuration Register = 00) START Read I/O7 - I/O0 Read I/O7 - I/O0 NO Toggle Bit = Toggle? YES NO I/O3, I/ YES Read I/O7 - I/O0 Twice Toggle Bit = NO Toggle? ...

Page 13

Status Bit Table I/O7 Configuration Register Programming I/O7 Erasing Erase Suspended & Read Erasing Sector Erase Suspended & Read DATA Non-erasing Sector Erase Suspended & I/O7 Program Non-erasing Sector Erase Suspended & Program Suspended and DATA Reading from Non- suspended ...

Page 14

Command Definition in Hex 1st Bus Cycle Command Bus Sequence Cycles Addr Read 1 Addr Chip Erase 6 555 Sector Erase 6 555 Word Program 4 555 (9) Dual Word Program 5 555 Enter Single Pulse 6 555 Program Mode ...

Page 15

Protection Register Addressing Table Word Use Block 0 Factory 1 Factory 2 Factory 3 Factory 4 User 5 User 6 User 7 User Note: All address lines not specified in the above table must be “0” when accessing the protection ...

Page 16

AT52BR1664A – Sector Address Table Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 ...

Page 17

... AT52BR1664AT – Sector Address Table Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 ...

Page 18

DC and AC Operating Range Operating Temperature (Case) V Power Supply CC Operating Modes Mode CE OE Read (2) Program/Erase Standby/Program Inhibit Program Inhibit Output ...

Page 19

DC Characteristics Symbol Parameter I Input Load Current LI I Output Leakage Current Standby Current CMOS Active Read Current Programming Current CC1 Input Load Current ...

Page 20

AC Read Characteristics Symbol Parameter t Read Cycle Time RC t Address to Output Delay ACC ( Output Delay CE ( Output Delay OE (3)( Output Float DF Output ...

Page 21

Input Test Waveforms and Measurement Level Output Test Load Pin Capacitance ( MHz 25° C Symbol Typ OUT Note: This parameter is characterized and is not 100% tested. 3361C–STKD–1/04 t ...

Page 22

AC Word Load Characteristics Symbol Parameter Address, OE Setup Time AS OES t Address Hold Time AH t Chip Select Setup Time CS t Chip Select Hold Time CH t Write Pulse Width (WE or CE) WP ...

Page 23

Program Cycle Characteristics Symbol Parameter t Word Programming Time BP t Word Programming Time in Dual Programming Mode BPD t Address Setup Time AS t Address Hold Time AH t Data Setup Time DS t Data Hold Time DH t ...

Page 24

Data Polling Characteristics Symbol Parameter t Data Hold Time Hold Time OEH ( Output Delay OE t Write Recovery Time WR Notes: 1. These parameters are characterized and not 100% tested. 2. See t ...

Page 25

Software Product Identification Entry LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 90 TO ADDRESS 555 ENTER PRODUCT IDENTIFICATION (2)(3)(5) MODE Software Product Identification Exit OR LOAD DATA AA TO ADDRESS 555 LOAD DATA ...

Page 26

The 4-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 256K words by 16 bits. The SRAM uses high-performance full CMOS process technology and is SRAM designed for high-speed and low-power circuit technology particularly well-suited ...

Page 27

Absolute Maximum Ratings Symbol Parameter Input/Output Voltage IN OUT V Power Supply CC T Operating Temperature A T Storage Temperature STG P Power Dissipation D Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may ...

Page 28

DC Electrical Characteristics T = -40° 85° Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Operating Power Supply Current CC I Average Operating Current CC1 I Standby Current (TTL Input) SB ...

Page 29

AC Characteristics T = -40° 85° C, Unless Otherwise Specified A # Symbol Parameter 1 t Read Cycle Time Address Access Time Chip Select Access Time ACS 4 t Output Enable to ...

Page 30

Output Test Load Note: 1. Including jig and scope capacitance. Timing Diagrams (1),(4) Read Cycle 1 ADDRESS SCS1 SCS2 SUB, SLB SOE DATA OUT (1) (2) ( Read Cycle 2 ADDRESS DATA OUT (1) (2) ( ...

Page 31

Write Cycle 1 (SWE Controlled) ADDRESS SCS1 SCS2 SUB, SLB SWE DATA IN DATA OUT Write Cycle 2 (SCS1, SCS2 Controlled) ADDRESS SCS1 SCS2 SUB, SLB SWE DATA IN  DATA OUT Notes write occurs during the overlap ...

Page 32

Data Retention Electric Characteristic T = -40° 85° Symbol Parameter V V for Data Retention Data Retention Current CCDR t Chip Deselect to Data CDR Retention Time t Operating Recovery Time R Note: ...

Page 33

... Plastic Chip-scale Ball Grid Array Package (CBGA) 3361C–STKD–1/04 Ordering Code Boot Block AT52BR1664AT-70CI Top AT52BR1664AT-90CI Top AT52BR1664A-70CI Bottom AT52BR1664A-90CI Bottom Package Type AT52BR1664A(T) Package Operation Range 66C5 Industrial (-40° to 85° C) 66C5 Industrial (-40° to 85° C) ...

Page 34

Packaging Information 66C5 – CBGA Marked A1 Identifier D Top View 0.60 REF Øb Bottom View 2325 Orchard Parkway San Jose, CA 95131 R AT52BR1664A( ...

Page 35

... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...

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