k4t1g084qc Samsung Semiconductor, Inc., k4t1g084qc Datasheet
k4t1g084qc
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k4t1g084qc Summary of contents
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... K4T1G044QC K4T1G084QC 1Gb C-die DDR2 SDRAM Specification 60FBGA & 84FBGA with Pb-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... K4T1G044QC K4T1G084QC Table of Contents 1.0 Ordering Information ................................................................................................................... 4 2.0 Key Features ................................................................................................................................. 4 3.0 Package Pinout/Mechanical Dimension & Addressing ............................................................ 5 3.1 x4 package pinout (Top View) : 60ball FBGA Package 3.2 x8 package pinout (Top View) : 60ball FBGA Package 3.3 FBGA Package Dimension(x4/x8) 4.0 Input/Output Functional Description .......................................................................................... 8 5.0 DDR2 SDRAM Addressing .......................................................................................................... 9 6.0 Absolute Maximum DC Ratings ................................................................................................ 10 7.0 AC & DC Operating Conditions ................................................................................................ 10 7 ...
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... K4T1G044QC K4T1G084QC Revision History Revision Month Year 1.0 March 2007 1.1 June 2007 - Initial Release - Added IDD values for DDR2-800 DDR2 SDRAM History Rev. 1.1 June 2007 ...
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... The 1Gb DDR2 device is available in 60ball FBGAs(x4/x8) Note : The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. 85°C, CASE DDR2 SDRAM DDR2-400 3-3-3 Package K4T1G044QC-ZC(L)CC 60 FBGA K4T1G084QC-ZC(L)CC 60 FBGA DDR2-400 3-3-3 Units 3 tCK Rev ...
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... K4T1G044QC K4T1G084QC 3.0 Package Pinout/Mechanical Dimension & Addressing 3.1 x4 package pinout (Top View) : 60ball FBGA Package VDD VDDQ VDDL BA2 VSS VDD Note : 1. Pin A3 has identical capacitance as pin A7. 2. VDDL and VSSDL are power and ground for the DLL. Ball Locations (x4 ...
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... K4T1G044QC K4T1G084QC 3.2 x8 package pinout (Top View) : 60ball FBGA Package 1 VDD DQ6 VDDQ DQ4 VDDL BA2 VSS VDD Note : 1. Pins B3 and A2 have identical capacitance as pins B7 and A8. 2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & DQS and input masking function is disabled. ...
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... K4T1G044QC K4T1G084QC 3.3 FBGA Package Dimension(x4/x8) MOLDING AREA 0.80 9 (Datum (Datum ∅0.45 Solder ball (Post reflow 0.50 ± 0.05 0. #A1 11.00 ± 0.10 A 0.80x8=6.40 3.20 #A1 MARK 1. (0.95) (1.90) 11.00 ± 0. DDR2 SDRAM B 0.35 ± 0.05 1.10 ± 0.10 Rev. 1.1 June 2007 ...
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... K4T1G044QC K4T1G084QC 4.0 Input/Output Functional Description Symbol Type Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of CK, CK Input the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing) ...
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... K4T1G044QC K4T1G084QC 5.0 DDR2 SDRAM Addressing 1Gb Addressing Configuration # of Bank Bank Address Auto precharge Row Address Column Address * Reference information: The following tables are address mapping information for other densities. 256Mb Configuration # of Bank Bank Address Auto precharge Row Address Column Address 512Mb ...
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... K4T1G044QC K4T1G084QC 6.0 Absolute Maximum DC Ratings Symbol Parameter Voltage on V pin relative Voltage on V pin relative DDQ DDQ Voltage on V pin relative DDL DDL Voltage on any pin relative IN, OUT T Storage Temperature STG Note : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... K4T1G044QC K4T1G084QC 7.2 Operating Temperature Condition Symbol TOPER Operating Temperature 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3 required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate ...
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... K4T1G044QC K4T1G084QC 7.6 Differential input AC logic Level Symbol Parameter V ID(AC) AC differential input voltage V AC differential cross point voltage IX(AC) Note : 1. V (AC) specifies the input differential voltage |V ID and V is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal ...
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... K4T1G044QC K4T1G084QC 9.0 OCD default characteristics Description Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Note : 1. Absolute Specifications (0°C ≤ T ≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V) CASE 2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ- 280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V ...
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... K4T1G044QC K4T1G084QC 10.0 IDD Specification Parameters and Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes Symbol Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; IDD0 Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current ...
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... K4T1G044QC K4T1G084QC Note : 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS bits 10 and 11 ...
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... CE6 LE6 CD5 LD5 155 140 155 130 180 ...
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... K4T1G044QC K4T1G084QC 12.0 Input/Output capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS 13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 (0 ° ...
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... K4T1G044QC K4T1G084QC 13.3 Timing Parameters by Speed Grade (Refer to notes for informations related to this table at the bottom) Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input hold time DQ and DM input setup time Control & ...
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... K4T1G044QC K4T1G084QC Parameter Exit active power down to read command Exit active power down to read command (slow exit, lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ...
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... K4T1G044QC K4T1G084QC 14.0 General notes, which may apply for all AC parameters 1. Slew Rate Measurement Levels a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV. ...
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... K4T1G044QC K4T1G084QC 4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent ...
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... K4T1G044QC K4T1G084QC 15.0 Specific Notes for dedicated AC parameters 9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing. ...
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... K4T1G044QC K4T1G084QC ∆tDS1, ∆tDH1 Derating Values for DDR2-400, DDR2-533(All units in ‘ps’; the note applies to the entire table) 2.0 V/ns 1.5 V/ns ∆tDS ∆tDH ∆tDS ∆tDH 2.0 188 188 167 146 1.5 146 167 125 125 1.0 63 125 0 Slew 0 rate 0 V/ns 0 0.5 - ...
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... K4T1G044QC K4T1G084QC 18. tIS and tIH (input setup and hold) derating. 2.0 V/ns ∆tIS 4.0 +187 3.5 +179 3.0 +167 2.5 +150 2.0 +125 1.5 +83 1.0 0 0.9 -11 Command/ Address Slew 0.8 -25 rate(V/ns) 0.7 -43 0.6 -67 0.5 -110 0.4 -175 0.3 -285 0.25 -350 0.2 -525 0.15 -800 2.0 V/ns ∆tIS 4.0 +150 3.5 +143 3.0 +133 2.5 +120 2.0 +100 1.5 +67 1.0 0 0.9 -5 Command/ 0.8 -13 Address Slew 0.7 -22 rate(V/ns) 0.6 -34 0.5 -60 0.4 -100 ...
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... K4T1G044QC K4T1G084QC 19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. MIN ( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH) ...
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... K4T1G044QC K4T1G084QC 29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V differential data strobe crosspoint for a rising signal, and from the input signal crossing at the V a falling signal applied to the device under test. ...