k4t1g084qm-zcd5 Samsung Semiconductor, Inc., k4t1g084qm-zcd5 Datasheet
k4t1g084qm-zcd5
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k4t1g084qm-zcd5 Summary of contents
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... M-die DDR2 SDRAM 1Gb M-die DDR2 SDRAM Specification Version 1.1 January 2005 Page DDR2 SDRAM Rev.1.1 Jan. 2005 ...
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... M-die DDR2 SDRAM Contents 0. Ordering Information 1. Key Feature 2. Package Pinout/Mechnical Dimension & Addressing 2.1 Package Pintout & Mechnical Dimension 2.2 Input/Output Function Description 2.3 Addressing 3. Absolute Maximum Rating 4. AC & DC Operating Conditions & Specifications Page DDR2 SDRAM Rev.1.1 Jan. 2005 ...
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... M-die DDR2 SDRAM 0. Ordering Information Organization DDR2-533 4-4-4 256Mx4 K4T1G044QM-ZCD5 128Mx8 K4T1G084QM-ZCD5 64Mx16 K4T1G164QM-ZCD5 Note : Speed bin is in order of CL-tRCD-tRP 1.Key Features DDR2-533 Speed 4-4-4 CAS Latency 4 tRCD(min) 15 tRP(min) 15 tRC(min) 55 • JEDEC standard 1.8V ± 0.1V Power Supply • VDDQ = 1.8V ± 0.1V • 200 MHz f ...
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... M-die DDR2 SDRAM 2. Package Pinout/Mechnical Dimension & Addressing 2.1 Package Pinout x4 package pinout (Top View) : 68ball FBGA Package 1 NC VDD NC VSSQ VDDQ NC VSSQ VDDL VREF BA2 A10/AP VSS VDD NC Ball Locations (x4) Top View (See the balls through the Package ...
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... M-die DDR2 SDRAM x8 package pinout (Top View) : 68ball FBGA Package 1 NC VDD RDQS DQ6 VSSQ VDDQ DQ4 VSSQ VDDL VREF BA2 A10/AP VSS VDD NC Ball Locations (x8) Top View (See the balls through the Package ...
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... M-die DDR2 SDRAM x16 package pinout (Top View) : 92ball FBGA Package 1 NC VDD DQ14 VSSQ VDDQ DQ12 VSSQ VDD DQ6 VSSQ VDDQ DQ4 VSSQ VDDL VREF BA2 A10/AP VSS VDD NC Ball Locations (x16) Top View (See the balls through the Package) ...
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... M-die DDR2 SDRAM FBGA Package Dimension(x4/x8) #A1 11.00 ± 0. INDEX MARK ...
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... M-die DDR2 SDRAM FBGA Package Dimension(x16) #A1 11.00 ± 0. INDEX MARK ...
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... Input Rank selection on systems with multiple Ranks considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM ODT Input signal for x4/x8 configurations. For x16 configuration, ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal ...
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... M-die DDR2 SDRAM 2.3 1Gb Addressing Configuration # of Bank Bank Address Auto precharge Row Address Column Address * Reference information: The following tables are address mapping information for other densities. 256Mb Configuration # of Bank Bank Address Auto precharge Row Address Column Address 512Mb Configuration ...
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... Exposure to absolute maximum rating conditions for extended periods may affect reli- ability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard & DC Operating Conditions Recommended DC Operating Conditions (SSTL - 1 ...
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... Parameter TOPER Operating Temperature 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3 required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate. ...
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... M-die DDR2 SDRAM Differential input AC logic Level Symbol Parameter V ID(AC) AC differential input voltage V IX(AC) AC differential cross point voltage Notes (AC) specifies the input differential voltage |V ID LDQS or UDQS) and V is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V ...
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... DRAM uncertainty. Output slew rate load : Output (V OUT) 7. DRAM output slew rate specification applies to 400Mb/sec/pin and 533Mb/sec/pin speed bins. 8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification. Min Nom Max 12 ...
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... M-die DDR2 SDRAM IDD Specification Parameters and Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes Symbol Proposed Conditions IDD0 Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands ...
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... M-die DDR2 SDRAM Notes : 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combi- nations of EMRS bits 10 and 11 ...
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... TBD IDD2N TBD IDD3P-F TBD IDD3P-S TBD IDD3N TBD IDD4W TBD IDD4R TBD IDD5B TBD IDD6 Normal TBD IDD7 TBD 128Mx8(K4T1G084QM) Symbol D5(DDR2-533@CL=4) CC(DDR2-400@CL=3) IDD0 TBD IDD1 TBD IDD2P TBD IDD2Q TBD IDD2N TBD IDD3P-F TBD IDD3P-S TBD IDD3N TBD IDD4W ...
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... M-die DDR2 SDRAM Input/Output capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS Electrical Characteristics & AC Timing for DDR2-533/400 (0 qC < ...
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... M-die DDR2 SDRAM Timing Parameters by Speed Grade (Refer to notes for informations related to this table at the bottom) Symbol Parameter DDR2-533 min DQ output access time tAC -500 from CK/CK DQS output access tDQSCK -450 time from CK/CK CK high-level width tCH 0.45 CK low-level width tCL 0.45 CK half period ...
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... M-die DDR2 SDRAM Symbol Parameter DDR2-533 min Mode register set tMRD 2 command cycle time Write postamble tWPST 0.4 Write preamble tWPRE 0.35 Address and control tIH(base) 375 input hold time Address and control tIS(base) 250 input setup time Read preamble tRPRE 0.9 Read postamble tRPST 0 ...
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... M-die DDR2 SDRAM Symbol Parameter DDR2-533 min Exit active power down tXARDS read command (slow exit, lower power) CKE minimum pulse t 3 CKE width (high and low pulse width) ODT turn-on delay t 2 AOND ODT turn-on tAC(mi t AON n) ODT turn-on(Power- ...
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... The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output tim- ing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. 3. DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as shown in the following figure. VDDQ ...
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... EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in sys- tem design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF ...
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... M-die DDR2 SDRAM Specific Notes for dedicated AC parameters 9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing ...
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... M-die DDR2 SDRAM 18. tIS and tIH (input setup and hold) derating. tIS, tIH Derating Values for DDR2-400, DDR2-533 2.0 V/ns 'tIS 4.0 +187 3.5 +179 3.0 +167 2.5 +150 2.0 +125 1.5 +83 1.0 0 Com- 0.9 -11 mand/Ad- dress Slew 0.8 -25 rate 0.7 -43 (V/ns) 0.6 -67 0.5 -110 0.4 -175 0.3 -285 0.25 -350 0.2 -525 0.15 -800 'tIS and 'tIH Derating Values for DDR2-667, DDR2-800 2 ...
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... M-die DDR2 SDRAM For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the datasheet tIS(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + delta tIS 19 ...
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... M-die DDR2 SDRAM culation is consistent. These notes are referenced in the “Timing parameters by speed grade” tables for DDR2-400/533/667 and DDR2-800. tHZ tRPST end point T2 T1 tHZ,tRPST = 2*T1-T2 end point <Test method for tLZ, tHZ, tRPRE and tRPST> 29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input sig- ...
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... M-die DDR2 SDRAM 31. Input waveform timing is referenced from the input signal crossing at the V and V for a falling signal applied to the device under test. IL(ac) 32. Input waveform timing is referenced from the input signal crossing at the V and V for a falling signal applied to the device under test. ...
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... M-die DDR2 SDRAM Revision History Version 0.1 (Feb. 2004) - Initial Release Version 0.2 (May 2004) - Corrected the Ordering Information Version 0.3 (Jul. 2004) - Corrected Typo Version 1.0 (Dec. 2004) - Added current values at DDR2-400 Version 1.1 (Jan. 2005) - Revised current test AC spec condition - Added derating table ...