k4d263238f Samsung Semiconductor, Inc., k4d263238f Datasheet

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k4d263238f

Manufacturer Part Number
k4d263238f
Description
1m X 32bit X 4 Banks Double Data Rate Synchronous Dram With Bi-directional Data Strobe And Dll
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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128M DDR SDRAM
K4D263238F
128Mbit DDR SDRAM
1M x 32Bit x 4 Banks
Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
Revision 1.1
May 2003
Rev 1.1 (May 2003)
- 1 -

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k4d263238f Summary of contents

Page 1

... K4D263238F 128Mbit DDR SDRAM Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL 1M x 32Bit x 4 Banks Revision 1.1 May 2003 - 1 - 128M DDR SDRAM Rev 1.1 (May 2003) ...

Page 2

... K4D263238F Revision History Revision 1.1 (May 30, 2003) • Added Lead Free package part number in the datasheet. Revision 1.0 (April 29, 2003) • Define DC spec. Revision 0.0 (January 20, 2003)- • Define target spec. Target spec - 2 - 128M DDR SDRAM Rev 1.1 (May 2003) ...

Page 3

... GENERAL DESCRIPTION FOR 1M x 32Bit x 4 Bank DDR SDRAM The K4D263238F is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized 1,048,576 words by 32 bits, fabricated with SAMSUNG s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance ...

Page 4

... K4D263238F PIN CONFIGURATION (Top View) DQ29 81 82 VSSQ 83 DQ30 DQ31 84 VSS 85 86 VDDQ N N.C N.C 90 N.C 91 VSSQ 92 93 RFU DQS 94 VDDQ 95 96 VDD DQ0 97 DQ1 98 99 VSSQ 100 DQ2 PIN DESCRIPTION CK,CK Differential Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe ...

Page 5

... K4D263238F INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type *1 Input CK, CK CKE Input CS Input RAS Input CAS Input WE Input DQS Input/Output Input Input/Output Input Input Power Supply Power Supply DDQ SSQ V Power Supply ...

Page 6

... K4D263238F BLOCK DIAGRAM (1Mbit x 32I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 32 Intput Buffer CK, CK Data Input Register Serial to parallel 64 1Mx32 1Mx32 1Mx32 1Mx32 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS ...

Page 7

... K4D263238F FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. ...

Page 8

... K4D263238F MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...

Page 9

... K4D263238F EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extend mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register) ...

Page 10

... K4D263238F ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. ...

Page 11

... K4D263238F DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T Parameter Symbol Operating Current I CC1 (One Bank Active) Precharge Standby Current I P CC2 in Power-down mode Precharge Standby Current I N CC2 in Non Power-down mode Active Standby Current I P CC3 power-down mode Active Standby Current in ...

Page 12

... K4D263238F AC OPERATING TEST CONDITIONS Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Output CAPACITANCE (V =2.5V Parameter ...

Page 13

... K4D263238F AC CHARACTERISTICS Parameter CK cycle time CL=3 CK high level width CK low level width DQS out access time from CK Output access time from CK Data strobe edge to Dout edge Read preamble Read postamble CK to valid DQS-in DQS-In setup time DQS-in hold time DQS write postamble ...

Page 14

... K4D263238F Note The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case ...

Page 15

... Note :1 For normal write operation, even numbers of Din are to be written inside DRAM AC CHARACTERISTICS (II) K4D263238F-QC40 Frequency Cas Latency 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 K4D623238F-QC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 183MHz ( 5.5ns ) 3 166MHz ( 6.0ns ) 3 * 183/166MHz were supported in K4D263238F-QC50 -40 Symbol Min Max tRC 15 - tRFC 17 - tRAS 10 100K tRCDRD 5 - tRCDWR ...

Page 16

... K4D263238F Simplified Timing(2) @ BL= ...

Page 17

... K4D263238F PACKAGE DIMENSIONS (TQFP) #100 #1 0.825 17.20 0.20 14.00 0.10 23.20 0.20 20.00 0.10 0.30 0.65 0.08 0.13 MAX 1.00 0.10 1.20 MAX * 0.10 MAX 0.05 MIN 0.80 0. 128M DDR SDRAM Dimensions in Millimeters 0.09~0.20 Rev 1.1 (May 2003) ...

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