k4d263238d Samsung Semiconductor, Inc., k4d263238d Datasheet
k4d263238d
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k4d263238d Summary of contents
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... K4D263238D 128Mbit DDR SDRAM Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL 1M x 32Bit x 4 Banks Revision 1.3 July 2002 - 1 - 128M DDR SDRAM Rev. 1.3 (Jul. 2002) ...
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... Changed power dissipation from 2.0W to 1.8W Revision 1.2 (June 17, 2002) • Removed K4D263238D-QC55 from the spec. • 183/166MHz were supported in K4D263238D-QC50. Revision 1.1 (May 24, 2002) • Removed K4D263238D-QC45/60 from the spec Revision 1.0 (May 20, 2002) • Define DC spec. Revision 0.0 (April 23, 2002)- • Define target spec. ...
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... GENERAL DESCRIPTION FOR 1M x 32Bit x 4 Bank DDR SDRAM The K4D263238D is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized 1,048,576 words by 32 bits, fabricated with SAMSUNG s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications ...
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... K4D263238D PIN CONFIGURATION (Top View) 81 DQ29 82 VSSQ 83 DQ30 84 DQ31 VSS 85 VDDQ 86 N.C 87 N.C 88 N N.C 92 VSSQ 93 RFU 94 DQS VDDQ 95 VDD 96 DQ0 97 DQ1 98 VSSQ 99 DQ2 100 PIN DESCRIPTION Differential Clock Input CK,CK CKE Clock Enable CS Chip Select RAS Row Address Strobe CAS Column Address Strobe ...
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... K4D263238D INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol *1 Input CK, CK CKE Input CS Input RAS Input CAS Input WE Input DQS Input/Output Input Input/Output Input Input Power Supply Power Supply DDQ SSQ V Power Supply REF ...
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... K4D263238D BLOCK DIAGRAM (1Mbit x 32I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 32 Intput Buffer CK, CK Data Input Register Serial to parallel 64 1Mx32 1Mx32 1Mx32 1Mx32 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS ...
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... K4D263238D FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. ...
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... K4D263238D MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...
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... K4D263238D EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extend mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register) ...
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... K4D263238D ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. ...
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... K4D263238D DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T Parameter Symbol Operating Current I CC1 (One Bank Active) Precharge Standby Current I P CC2 in Power-down mode Precharge Standby Current I N CC2 in Non Power-down mode Active Standby Current I P CC3 power-down mode Active Standby Current in ...
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... K4D263238D AC OPERATING TEST CONDITIONS Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Output CAPACITANCE (V =2.5V Parameter ...
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... K4D263238D AC CHARACTERISTICS Parameter CL=3 CK cycle time CL=4 CK high level width CK low level width DQS out access time from CK Output access time from CK Data strobe edge to Dout edge Read preamble Read postamble CK to valid DQS-in DQS-In setup time DQS-in hold time DQS write postamble ...
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... K4D263238D Note The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case ...
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... K4D263238D AC CHARACTERISTICS (I) Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Row active to Row active Last data in to Row precharge Last data in to Read command Col. address to Col. address ...
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... K4D263238D AC CHARACTERISTICS (II) K4D263238D-QC40 Frequency Cas Latency 250MHz ( 4.0ns ) 4 200MHz ( 5.0ns ) 3 K4D623238F-QC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 183MHz ( 5.5ns ) 3 166MHz ( 6.0ns ) 3 * 183/166MHz were supported in K4D263238D-QC50 tRC tRFC tRAS tRCDRD tRCDWR tRC tRFC tRAS tRCDRD tRCDWR ...
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... K4D263238D Simplified Timing(2) @ BL= ...
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... K4D263238D PACKAGE DIMENSIONS (TQFP) #100 #1 0.825 17.20 0.20 14.00 0.10 23.20 0.20 20.00 0.10 0.30 0.65 0.08 0.13 MAX 1.00 0.10 1.20 MAX * 0.10 MAX 0.05 MIN 0.80 0. 128M DDR SDRAM Dimensions in Millimeters 0.09~0.20 Rev. 1.3 (Jul. 2002) ...