hb28d032bp2 Renesas Electronics Corporation., hb28d032bp2 Datasheet

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hb28d032bp2

Manufacturer Part Number
hb28d032bp2
Description
Mobile Embedded Flash With Multimediacard-tm Interface 16 Mbyte/32 Mbyte
Manufacturer
Renesas Electronics Corporation.
Datasheet
Description
The HB28E016BP2 and HB28D032BP2 are Hitachi Mobile Embedded Flashes with MultiMediaCard
interface, which are highly integrated flash memories with serial and random access capability. It is
accessible via a dedicated serial interface optimized for fast and reliable data transmission. This interface
allows several cards to be stacked by through connecting their peripheral contacts. These Hitachi Mobile
Embedded Flashes are fully compatible to a new consumer standard, called the MultiMediaCard system
standard defined in the MultiMediaCard system specification [1], except the physical outline and the pin
assignment. The MultiMediaCard system is a new mass-storage system based on innovations in
semiconductor technology. It has been developed to provide an inexpensive, mechanically robust storage
medium in card form for multimedia consumer applications. These Hitachi Mobile Embedded Flashes
allow the design of inexpensive players and drives without moving parts. A low power consumption and a
wide supply voltage range favors mobile, battery-powered applications such as audio players, organizers,
palmtops, electronic books, encyclopedia and dictionaries. Using very effective data compression schemes
such as MPEG, these Hitachi Mobile Embedded Flashes will deliver enough capacity for all kinds of
multimedia data: software/programs, text, music, speech, images, video etc.
Note: MultiMediaCard
Features
Preliminary: The specification of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specification.
16 MByte/32 MByte memory capacity
On card error correction
Mobile Embedded Flash with MultiMediaCard
HB28E016BP2/HB28D032BP2
is a trademark of Infineon Technologies AG.
16 Mbyte/32 Mbyte
ADE-203-1293A (Z)
Interface
Nov. 5, 2001
Preliminary
Rev. 0.1
TM

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hb28d032bp2 Summary of contents

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... Mobile Embedded Flash with MultiMediaCard Description The HB28E016BP2 and HB28D032BP2 are Hitachi Mobile Embedded Flashes with MultiMediaCard interface, which are highly integrated flash memories with serial and random access capability accessible via a dedicated serial interface optimized for fast and reliable data transmission. This interface allows several cards to be stacked by through connecting their peripheral contacts ...

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HB28E016/D032BP2 MultiMediaCard system standard compatibility System specification version 3.1 compliant SPI mode supports the single and multiple block read and write operations. Block and partial block read supported (Command classes 2) Stream read supported (Command class 1) Block write and ...

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Pin Arrangement SS2 SS1 RSV CLK CMD DAT (Top view) HB28E016/D032BP2 ...

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HB28E016/D032BP2 Block Diagram V PP Generator Flash control All units in these Hitachi Mobile Embedded Flashes are clocked by an internal clock generator. The Interface driver unit synchronizes the DAT and CMD signals from external CLK to the internal used ...

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Interface These Hitachi Mobile Embedded Flashes' interface can operate in two different modes: MultiMediaCard mode SPI mode Both modes are using the same pins. The default mode is the MultiMediaCard mode. The SPI mode is selected by activating (= 0) ...

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HB28E016/D032BP2 MultiMediaCard Mode Pad Definition Pin No. Name Type*1 C7 RSV NC E8 CMD I/O/PP/ SS1 D10 CLK SS2 F6 DAT I/O/PP Note power supply; I: input; ...

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SPI Mode The Serial Peripheral Interface (SPI general-purpose synchronous serial interface originally found on certain Motorola microcontrollers. These Hitachi Mobile Embedded Flashes SPI interface is compatible with SPI hosts available on the market. As any other SPI device ...

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HB28E016/D032BP2 SPI Interface Pin Configuration MuitiMediaCard mode Pin No. Name Type*1 Description C7 RSV NC Reserved for future use CS E8 CMD I/O/PP/OD Command/Response Ground SS1 D10 V S Power supply CC D5 CLK I Clock D3 ...

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Registers These Hitachi Mobile Embedded Flashes contain the following information registers: Name Width Type OCR 32 Programmed by the manufacturer. Read only for user CID 128 Programmed by the manufacturer. Read only for user RCA 16 Programmed during initialization, not ...

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HB28E016/D032BP2 Operation Condition Register (OCR) This register indicates supported voltage range of these Hitachi Mobile Embedded Flashes bit wide register and for read only. OCR Fields OCR slice D31 D[30-24] D23 D22 D21 D20 D19 D18 ...

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Card Identification (CID) This register contains the card identification information used during the card identification procedure 128 bit wide register, one-time programmable by the provider. The CID is divided into eight slices: CID Fields Name Field Manufacturer ...

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HB28E016/D032BP2 Card Specific Data (CSD) The card specific data register describes how to access the card content. The CSD defines card operating parameters like maximum data access time, data transfer speed. The CSD Fields Name Field CSD structure CSD_STRUCTURE Spec ...

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Name Field Write protect group size WP_GRP_SIZE Write protect group enable WP_GRP_ENABLE Manufacturer default ECC DEFAULT_ECC Write speed factor R2W_FACTOR Max. write data block length WRITE_BLK_LEN Partial blocks for write allowed WRITE_BLK_PARTIAL Reserved — File format group FILE_FORMAT_GRP Copy flag ...

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HB28E016/D032BP2 SPEC_VERS Defines the Spec version supported by the card. It includes the commands set definition and the definition of the card responses. The card identification procedure is compatible for all spec versions! SPEC Version SPEC_VERS ”0011” The Spec version ...

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TRAN_SPEED The following table defines the maximum data transfer rate TRAN_SPEED: Maximum Data Transfer Rate Definition TRAN_SPEED bit Description 2:0 transfer rate exponent 6:3 time mantissa 7 reserved These Hitachi Mobile Embedded Flashes support a transfer rate between 0 and ...

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HB28E016/D032BP2 READ_BLK_LEN The data block length is computed as 2 Data Block Length READ_BLK_LEN Block length byte bytes ...... ...... 2048 bytes 12–15 reserved The block ...

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... READ_BLK_LEN BLOCK_LEN = 2 , (READ_BLK_LEN Therefore, the maximal capacity which can be coded is 4096*512*2048 = 4 GBytes. The following table shows the card capacity for each model. Model C_SIZE HB28E016BP2 0x7A7 HB28D032BP2 0x7A7 For more detailes refer to Chapater “Characteristics”. HB28E016/D032BP2 8) 12) C_SIZE_MULT READ_BLK_LEN ...

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... The parameter VDD_R_CURR_MAX and VDD_W_CURR_MAX are permanently assigned. The value of VDD_R_CURR_MAX and VDD_W_CURR_MAX for each model is following; Model Value HB28E016BP2 6 (80 mA) HB28D032BP2 6 (80 mA) For more detailes refer to Chapter “Characteristics”. C_SIZE_MULT This parameter is used for coding a factor MULT for computing the total device size (refer to “C_SIZE”). C_SIZE_MULT+2 ...

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Multiply Factor for the Device Size C_SIZE_MULT MULT 128 8 6 ...

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HB28E016/D032BP2 Set by the card manufacturer and defines the ECC code which is recommended to use (e.g. the device is tested for). The value is set to ‘0’, indicating that no designated ECC is recommended. R2W_FACTOR Defines the typical block ...

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WRITE_BLK_LEN The data block length is computed as 2 Data Block Length WRITE_BLK_LEN Block length byte bytes ...... ...... 2048 bytes 12–15 reserved The block length ...

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HB28E016/D032BP2 TMP_WRITE_PROTECT Temporarily protects the whole card content from being overwritten or erased (all write and erase commands for this card are temporarily disabled). This parameter is programmable by the customer. The default value is ‘0’ (not protected). FILE_FORMAT Indicates ...

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MultiMediaCard Communication All communication between host and cards is controlled by the host (master). The host sends commands and, depending on the command, receives a corresponding response from the selected card. In this chapter the commands to control these Hitachi ...

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HB28E016/D032BP2 Hitachi Mobile Embedded Flash ERASE GROUP 0 ERASE GROUP 1 ERASE GROUP n Each WP-group may have an additional write protection bit. The write protection bits are programmable via special commands (refer to Chapter “Commands”). The information about the ...

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Commands The command set of the MultiMediaCard system is divided into classes corresponding to the type of card (see also [1]). These Hitachi Mobile Embedded Flashes support the following command classes: Command Classes (Class 0 to Class 2 and Class ...

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HB28E016/D032BP2 The command transmission always starts with the MSB. Each command starts with a start bit and ends with a 7-bit CRC command protection field followed by an end bit. The length of each command frame is fixed to 48 ...

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Read, Write and Erase Time-out Conditions The times after which a time-out condition for read/write/erase operations occurs are (card independent) 10 times longer than the access/program times for these operations given below. A card shall complete the command within this ...

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HB28E016/D032BP2 Basic Commands (class 0) and Read Stream Command (class 1) CMD index Type Argument CMD0 bc [31:0] stuff bits CMD1 bcr [31:0] OCR without busy CMD2 bcr [31:0] stuff bits CMD3 ac [31:16] RCA [15:0] stuff bits CMD4 bc ...

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Block-Oriented Read Commands (class 2) CMD index Type Argument CMD16 ac [31:0] block length CMD17 adtc [31:0] data address CMD18 adtc [31:0] data address Notes: 1. The default block length is as specified in the CSD. 2. The data transferred ...

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... BLOCK a STOP_TRANSMISSION follows. R1 PROGRAM_CID Programming of the card identification register. This command is only done once per Hitachi Mobile Embedded Flash card. The card has some hardware to prevent this operation after the first programming. Normally this command is reserved for the manufacturer. R1 PROGRAM_CSD Programming of the programmable bits of the CSD ...

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Write Protection Commands (class 6) CMD index Type Argument Resp Abbreviation CMD28 ac [31:0] data R1b address CMD29 ac [31:0] data R1b address CMD30 adtc [31:0] write R1 protect data address Note write protection bits (representing 32 write ...

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HB28E016/D032BP2 Other Command CMD index Type Argument CMD5 reserved CMD6 reserved CMD8 reserved CMD14 reserved CMD19 reserved CMD21... reserved CMD22 CMD31 reserved CMD39 Not supported CMD40 Not supported CMD41 reserved CMD43... reserved CMD54 CMD55 ac [31:16] RCA [15:0] stuff bits ...

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Card identification mode All the data communication in the card identification mode uses only the command line (CMD). Power on Idle state (idle) card is busy or host omitted voltage range CMD1 card looses bus Ready state (ready) CMD2 Identification ...

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HB28E016/D032BP2 bits do not match the corresponding bits on the command line in any one of the bit periods, stop sending their CID immediately and must wait for the next identification cycle (cards stay in the Ready State). There should ...

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Data Transfer Mode When in Standby State, both CMD and DAT lines are in the push-pull mode. As long as the content of all CSD registers is not known, the f PP allows the host to get the Card Specific ...

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HB28E016/D032BP2 with an end bit (HIGH). The data transmission is synchronous to the clock signal. The payload for block- oriented data transfer is preserved by a 16-bit CRC check sum (refer to Chapter “Cyclic Redundancy Check (CRC)”). Stream read There ...

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The read error is reported in the response to the stop transmission command. If the host sends a stop transmission command after the card transmits the last block of a ...

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HB28E016/D032BP2 terminated with an error. In order to start a multiple block write with pre-defined block count the host must use the SET_BLOCK_COUNT command (CMD23) immediately preceding the WRITE_MULTIPLE_BLOCK (CMD25) command. Otherwise the card will start an open-ended multiple block ...

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DAT low. The actual erase time may be quite long, and the host may choose to deselect the card using CMD7. Write protect management Card data may be protected against either erase or write. The entire card may be ...

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HB28E016/D032BP2 SET_PWD Set new password to PWD PWD_LEN: Defines the following password length (in bytes). PWD: The password (new or currently used depending on the command). The data block size shall be defined by the host before it ...

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—Define the block length (CMD16), given by the 8 bit card lock/unlock mode, the 8 bit password size (in bytes), and the number of bytes of the currently used password. —Send the card lock/unlock command with the appropriate data block ...

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HB28E016/D032BP2 State transition summary Table “Card State Transition Table” defines the card state transitions as a function of received command Card State Transition Table Current state Command idle 1 CRC fail —* Commands out of the — supported class(es) Class0 ...

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Current state Command idle Class4 CMD16 CMD23 CMD24 — CMD25 — CMD26 — CMD27 — Class5 CMD32 — CMD33 — CMD34 — CMD35 — CMD36 — CMD37 — CMD38 — Class6 CMD28 — CMD29 — CMD30 — Class7 CMD42 — ...

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HB28E016/D032BP2 Responses All responses are sent via command line (CMD), all data starts with the MSB. Format R1 (response command): response length 48 bit start bit card The contents of the status field are described in Chapter “Status” ...

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Status The response format R1 contains a 32-bit field with the name card status. This field is intended to transmit status information which is stored in a local status register of each card to the host. The following table defines ...

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HB28E016/D032BP2 Status Bits Identifier Type Value 31 OUT_OF_RANGE ADDRESS_ERROR ’0’= no error 29 BLOCK_LEN_ERROR ERASE_SEQ_ERROR ERASE_PARAM WP_VIOLATION ’0’= not protected 25 CARD_IS_LOCKED ...

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Bits Identifier Type Value 16 CID_OVERWRITE ’0’= no error CSD_OVERWRITE 15 WP_ERASE_SKIP CARD_ECC_ S X DISABLED 13 ERASE_RESET S R 12:9 CURRENT_STATE BUFFER_EMPTY S X 7:6 reserved 5 APP_CMD S R ...

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HB28E016/D032BP2 Command Response Timings All timing diagrams use the following schematics and abbreviations: S: Start bit (= 0) T: Transmitter bit (Host = 1, Card = 0) P: One-cycle pull- End bit (= 1) Z: high impedance ...

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The host command and the card response are clocked out with the rising edge of the host clock. The delay between host command and card response is N for host command CMD3: Host command CMD S T content Host active ...

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HB28E016/D032BP2 Last host command - next host command timing diagram After the last command, which does not force a response, has been sent, the host can continue sending the next command after at least N clock periods. CC Host command ...

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Stream read The data transfer starts N clock cycles after the end bit of the host command. The bus transaction is AC identical to that of a read block command (refer to Figure “Data Read Timing”). As the data transfer ...

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HB28E016/D032BP2 Stream write The data transfer starts N clock cycles after the card response to the sequential write command was WR received. The bus transaction is identical to that of a write block command (see Figure “Timing of The Block ...

Page 53

Reset GO_IDLE_STATE (CMD0) is the software reset command, which sets these Hitachi Mobile Embedded Flashes into the Idle State independently of the current state. In the Inactive State these Hitachi Mobile Embedded Flashes are not affected by this command. After ...

Page 54

HB28E016/D032BP2 SPI Communication The SPI mode consists of a secondary communication protocol. MultiMediaCard protocol, designed to communicate with a SPI channel, commonly found in Motorola’s (and lately a few other vendors’) microcontrollers. The interface is selected during the first reset ...

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Bus Transfer Protection Every MultiMediaCard token transferred on the bus is protected by CRC bits. In SPI mode, these Hitachi Mobile Embedded Flashes offer a non-protected mode which enables systems built with reliable data links to exclude the hardware or ...

Page 56

HB28E016/D032BP2 Redundancy Check (CRC)”). CMD17 (READ_SINGLE_BLOCK) initiates a single block read. CMD18 (READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks. Two types of multiple block read transactions are defined (the host can use either one at any time): • Open-ended ...

Page 57

Data in command Data out response After a data block has been received, the card will respond with a data-response token. If the data block has been received without errors, it will be programmed. As long ...

Page 58

HB28E016/D032BP2 failure in the data-response token and ignore any further incoming data blocks. The host must than abort the operation by sending the ‘Stop Tran’ token. If the host uses partial blocks whose accumulated length is not block aligned and ...

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Erase and Write Protect Management The erase and write protect management procedures in the SPI mode are identical to those of the MultiMediaCard mode. While the card is erasing or changing the write protection bits of the predefined sector list, ...

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HB28E016/D032BP2 Error Conditions Unlike the MultiMediaCard protocol, in the SPI mode the card will always respond to a command. The response indicates acceptance or rejection of the command. A command may be rejected not supported (illegal opcode), ...

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Commands and Arguments CMD index SPI mode Argument CMD0 Yes None CMD1 Yes None CMD2 No CMD3 No CMD4 No CMD5 reserved CMD6 reserved CMD7 No CMD8 reserved CMD9 Yes None CMD10 Yes None CMD11 No CMD12 Yes None CMD13 ...

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HB28E016/D032BP2 CMD index SPI mode Argument CMD24 Yes [31:0] data address CMD25 Yes [31:0] data address CMD26 No CMD27 Yes None CMD28 Yes [31:0] data address CMD29 Yes [31:0] data address CMD30 Yes [31:0] write protect data address CMD31 reserved ...

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CMD index SPI mode Argument CMD41 reserved CMD42 Yes [31:0] stuff bits CMD43... reserved CMD54 CMD55 (Yes) [31:16] RCA [15:0] stuff bits CMD56 (Yes) [31:1] stuff bits [0:0] RD/WR* CMD57 reserved CMD58 Yes None CMD59 Yes [31:1] stuff bits [0:0] ...

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HB28E016/D032BP2 Responses There are several types of response tokens the MultiMediaCard mode, all are transmitted MSB first: Format R1 This response token is sent by the card after every command with the exception of SEND_STATUS commands ...

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Format R2 This response token is two bytes long and sent as a response to the SEND_STATUS command. The format is given in Figure “R2 Response Format”. 1. Byte The first byte is identical to the ...

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HB28E016/D032BP2 Format R3 This response token is sent by the card when a READ_OCR command is received. The response length is 5 bytes (refer to Figure “R3 Response Format”). The structure of the first (MSB) byte is identical to response ...

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Last two bytes: 16-bit CRC. Data Error Token If a read operation fails and the card cannot provide the required data, it will send a data error token instead. This token is one byte long and has the following format: ...

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HB28E016/D032BP2 Clearing Status Bits As described in the previous paragraphs, in SPI mode, status bits are reported to the host in three different formats: response R1, response R2 and data error token (the same bits may exist in multiple response ...

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Identifier Included Type in resp Illegal command Card ECC failed DataErr CC error DataErr Error DataErr WP erase skip Lock/Unlock R2 E ...

Page 70

HB28E016/D032BP2 SPI Bus Timing All timing diagrams use the following schematics and abbreviations: H: Signal is high (logical ‘1’) L: Signal is low (logical ‘0’) X: Don’t care Z: High impedance state (-> Repeater Busy: Busy Token ...

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Card Response to Host Command Datain Dataout bytes response Single Block ...

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HB28E016/D032BP2 Single Block Write Datain Write command Dataout Z Z ...

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Error Handling These Hitachi Mobile Embedded Flashes are defined as error free devices or as devices with a defined maximum bit error rate (with external error correction circuitry). To correct defects in the memory field of the cards the system ...

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HB28E016/D032BP2 All CRC registers are initialized to zero. The first bit is the first data bit of the corresponding block. The degree n of the polynomial denotes the number of bits of the data block decreased by one (e.g. n ...

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Power Supply Power Supply Decoupling The and V lines supply the card with operating voltage. For this, decoupling capacitors for SS1 SS2 CC buffering current peak are used. These capacitors are placed on the bus side corresponding ...

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HB28E016/D032BP2 Power on Each card has its own power on detection circuitry which puts the card into a defined state after the power- on. No explicit reset signal is necessary. The cards can also be reset by a special software ...

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V Bus master supply voltage 2.7 V 2.0 V Power up time Supply ramp up time Initialization sequence Initialization delay: The maximum of 1 msec, 74 clock cycles and supply ramp up time After power up these Hitachi Mobile ...

Page 78

HB28E016/D032BP2 Short Cut Protection If one of the supply pins ( line to supply the card. Naturally the card can not operate properly under this conditions CMD, DAT Every ...

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Characteristics This chapter defines following characteristics: Temperature characteristics Electrical characteristics Temperature Characteristics Parameter Symbol Storage temperature Operating temperature Junction temperature Electrical Characteristics In this chapter the electrical characteristics for these Hitachi Mobile Embedded Flashes are defined in three steps: Pad ...

Page 80

HB28E016/D032BP2 Absolute Maximum Ratings Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not ...

Page 81

Recommended Operating Conditions The recommended operating conditions define the parameter ranges for optimal performance and durability of these Hitachi Mobile Embedded Flashes. Parameter Supply voltage Inputs Low-level input voltage V High-level input voltage V Outputs High-level output current Low-level output ...

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HB28E016/D032BP2 Recommended Bus Conditions Parameter Clock Pull-up resistance for input clk CMD Pull-up resistance for DAT R Bus signal line capacitance Maximum signal line inductance Operating Characteristics The operating characteristics are parameters measured in a MultiMediaCard system assuming the recommended ...

Page 83

... Parameter High speed supply HB28E016BP2 current HB28D032BP2 Minimal supply HB28E016BP2 current HB28D032BP2 All digital inputs Input leakage current (Including I/O current) All outputs High-level output voltage Low-level output voltage Inputs: CMD, DAT Input set-up time (Referred to CLK), DI (Referred to SCLK), CS Input hold time ...

Page 84

HB28E016/D032BP2 Clock Input Valid data Output : Invalid Timing Diagram of Data Input and Output The access time ( divided into two parts The synchronous access time. This time defines the time of the maximum ...

Page 85

Access Time Parameter Synchronous access delay cycles Synchronous access delay Asynchronous access delay Memory access time Note: 1. Refer to Chapter “Time-out Condition”. In the CSD are two fields to code the asynchronous and the synchronous access delay time: TAAC, ...

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HB28E016/D032BP2 Abbreviations and Terms Abbreviations Terms <n> Argument of a command or data field. CMD<n> MultiMediaCard bus command <n>. See Command. PP Push Pull, output driver type with low impedance driver capability for 0 and 1. OD Open Drain, output ...

Page 87

Abbreviations Terms CIN Card individual number. CRC Cyclic redundancy check. ECC Error correction code. G(x) Generator polynomial of error correction/check code. TAC Asynchronous access delay NSAC Number of synchronous access cycles to be added to the access delay f Open ...

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HB28E016/D032BP2 Physical Outline (HB28E016BP2) 9.00 0. INDEX 0.15 4 0. 0.45 0.08 S Details of the part A Datum A, B are defined as center lines of ...

Page 89

... Physical Outline (HB28D032BP2) 10.00 0. INDEX 0.15 4 0.20 S 0. 0.45 0.08 S Details of the part A Datum A, B are defined as center lines of ball matrix. Sn-Ag-Cu alloy were used for ball material. Hitachi Code JEDEC Code EIAJ Code Mass (reference value) HB28E016/D032BP2 Unit 2. ...

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HB28E016/D032BP2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may ...

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