hb28j128mm3 Renesas Electronics Corporation., hb28j128mm3 Datasheet
hb28j128mm3
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hb28j128mm3 Summary of contents
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... Description These Renesas MultiMediaCards, HB28K032MM3, HB28K032RM3, HB28L064MM3, HB28L064RM3, HB28J128MM3, HB28J128RM3, HB28J256MM3, HB28J256RM3 and HB28J512MM3 are highly integrated flash memories with serial and random access capability accessible via a dedicated serial interface optimized for fast and reliable data transmission. This interface allows several cards to be stacked by through connecting their peripheral contacts ...
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... HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Features MultiMediaCard line up: Model HB28K032MM3 HB28K032RM3 HB28L064MM3 HB28L064RM3 HB28J128MM3 HB28J128RM3 HB28J256MM3 HB28J256RM3 HB28J512MM3 Note: 1. Refer to Chapter “Physical Outline”. On card error correction MultiMediaCard system standard compatibility System specification version 3.3 compliant SPI mode supports the single and multiple block read and write operations. ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Block Diagram V PP Generator Flash control All units in these Renesas MultiMediaCards are clocked by an internal clock generator. The Interface driver unit synchronizes the DAT and CMD signals from external CLK to the internal used clock ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Interface These Renesas MultiMediaCards' interface can operate in two different modes: MultiMediaCard mode SPI mode Both modes are using the same pins. The default mode is the MultiMediaCard mode. The SPI mode is selected by activating (= 0) ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 MultiMediaCard Mode Pad Definition Pin No. Name Type* 1 RSV NC 2 CMD I/O/PP/ SS1 CLK SS2 7 DAT I/O/PP Note power supply; I: ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 SPI Mode The Serial Peripheral Interface (SPI general-purpose synchronous serial interface originally found on certain Motorola microcontrollers. The MultiMediaCard SPI interface is compatible with SPI hosts available on the market. As any other SPI device the ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 SPI Interface Pin Configuration MultiMediaCard 1 Pin No. Name Type* Description 1 RSV NC Reserved for future use CS 2 CMD I/O/PP/OD Command/Response Ground SS1 Power supply CC 5 CLK I Clock ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Registers These Renesas MultiMediaCards contain the following information registers: Name Width Type OCR 32 Programmed by the manufacturer. Read only for user. CID 128 Programmed by the manufacturer. Read only for user. RCA 16 Programmed during initialization, not ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Operation Condition Register (OCR) This register indicates supported voltage range of these Renesas MultiMediaCards bit wide register and for read only. OCR Fields OCR slice Field D31 Card power up status bit (Busy). D[30-24] ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Card Identification (CID) This register contains the card identification information used during the card identification procedure 128 bit wide register, one-time programmable by the provider. It was programmed at the manufacturer. The CID is divided ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Card Specific Data (CSD) The card specific data register describes how to access the card content. The CSD defines card operating parameters like maximum data access time, data transfer speed. The CSD Fields Name Field CSD structure CSD_STRUCTURE ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Name Field Write protect group size WP_GRP_SIZE Write protect group enable WP_GRP_ENABLE Manufacturer default ECC DEFAULT_ECC Write speed factor R2W_FACTOR Max. write data block length WRITE_BLK_LEN Partial blocks for write WRITE_BLK_PARTIAL 1 allowed Reserved Content protection application CONTENT_PROT_AP ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 SPEC_VERS Defines the Spec version supported by the card. It includes the commands set definition and the definition of the card responses. The card identification procedure is compatible for all spec versions! SPEC Version SPEC_VERS “0011” The Spec ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 TRAN_SPEED The following table defines the maximum data transfer rate TRAN_SPEED: Maximum Data Transfer Rate Definition TRAN_SPEED bit Description 2:0 Transfer rate exponent 6:3 Time mantissa 7 Reserved These Renesas MultiMediaCards support a transfer rate between 0 and ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 READ_BLK_LEN The data block length is computed as 2 Data Block Length READ_BLK_LEN Block length byte bytes ...... ...... 2048 bytes 12 15 Reserved ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 DSR_IMP Defines if the configurable driver stage option is integrated on the card or not. If implemented a driver stage register (DSR) must be implemented also. DSR Implementation DSR_IMP DSR type 0 No DSR implemented 1 DSR implemented ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 VDD_R_CURR_MIN, VDD_W_CURR_MIN The maximum supply current at the minimum supply voltage V Maximum Supply Current Consumption at V VDD_R_CURR_MIN VDD_W_CURR_MIN Code for current consumption at 2 0 ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Card Capacity 32 MByte 64 MByte 128 MByte 256 MByte 512 MByte For more details refer to Chapter “Characteristics”. C_SIZE_MULT This parameter is used for coding a factor MULT for computing the total device size (refer to “C_SIZE”). ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 ERASE_GRP_MULT A 5 bit binary coded value is used for calculating the size of the erasable unit of these Renesas MultiMediaCards. The parameter ERASE_GRP_MULT is permanently assigned to the value 0x0F. See ERASE_GRP_SIZE section for detailed description. WP_GRP_SIZE ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 WRITE_BLK_LEN The data block length is computed as 2 Data Block Length WRITE_BLK_LEN Block length byte bytes ...... ...... 2048 bytes 12 15 Reserved ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 COPY Defines if the contents are an original (COPY = ‘0’ copy (= ‘1’). The COPY bit is a one time programmable bit, being set by the customer. The default value is ‘0’. PERM_WRITE_PROTECT Permanently protects ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 ECC Defines the ECC code that was used for storing data on the card. This field is used by the host (or application) to decode the user data. The following table defines the field format. ECC ECC ECC ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 MultiMediaCard Communication All communication between host and cards is controlled by the host (master). The host sends commands and, depending on the command, receives a corresponding response from the selected card. In this chapter the commands to control ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 MultiMediaCard ERASE GROUP 0 ERASE GROUP 1 ERASE GROUP n Each WP-group may have an additional write protection bit. The write protection bits are programmable via special commands (refer to Chapter “Commands”). The information about the availability is ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Commands The command set of the MultiMediaCard system is divided into classes corresponding to the type of card (see also [1]). These Renesas MultiMediaCards support the following command classes: Command Classes (class 0 to class 2) Card command ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 The command transmission always starts with the MSB. Each command starts with a start bit and ends with a 7-bit CRC command protection field followed by an end bit. The length of each command frame is fixed to ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Read, Write and Erase Time-out Conditions The times after which a time-out condition for read/write/erase operations occurs are (card independent) 10 times longer than the access/program times for these operations given below. A card shall complete the command ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Basic Commands (class 0) and Read Stream Command (class 1) CMD index Type Argument Resp CMD0 bc [31:0] stuff bits CMD1 bcr [31:0] OCR R3 without busy CMD2 bcr [31:0] stuff bits R2 CMD3 ac [31:16] RCA R1 ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Block-Oriented Read Commands (class 2) CMD index Type Argument Resp CMD16 ac [31:0] block R1 length CMD17 adtc [31:0] data R1 address CMD18 adtc [31:0] data R1 address Notes: 1. The default block length is as specified in ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Block-Oriented Write Commands (class 4) CMD index Type Argument Resp CMD24 adtc [31:0] data R1 address CMD25 adtc [31:0] data R1 address CMD26 adtc [31:0] stuff bits R1 CMD27 adtc [31:0] stuff bits R1 Note: 1. The data ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Write Protection Commands (class 6) CMD index Type Argument Resp CMD28 ac [31:0] data R1b address CMD29 ac [31:0] data R1b address CMD30 adtc [31:0] write R1 protect data address Note write protection bits (representing 32 ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Other Command CMD index Type Argument CMD5 Reserved CMD6 Reserved CMD8 Reserved CMD14 Reserved CMD19 Reserved CMD21 … Reserved CMD22 CMD31 Reserved CMD39 Not supported CMD40 Not supported CMD41 Reserved CMD43 … Reserved CMD54 CMD55 ac [31:16] RCA ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Card identification mode All the data communication in the card identification mode uses only the command line (CMD). Power on Idle state (idle) card is busy or host omitted voltage range CMD1 card loses bus Ready state (ready) ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 their CID immediately and must wait for the next identification cycle (cards stay in the Ready State). There should be only one card which successfully sends its full CID-number to the host. This card then goes into the ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Data Transfer Mode When in Standby State, both CMD and DAT lines are in the push-pull mode. As long as the content of all CSD registers is not known, the f clock rate is equal to the slow ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 ends with an end bit (HIGH). The data transmission is synchronous to the clock signal. The payload for block-oriented data transfer is preserved by a 16-bit CRC check sum (refer to Chapter “Cyclic Redundancy Check (CRC)”). Stream read ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 If the card detects an error (e.g. out of range, address misalignment, internal error, etc.) during a multiple block read operation (both types) it will stop data transmission and remain in the Data State. The host must than ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Multiple block write with pre-defined block count The card will transfer the requested number of data blocks, terminate the transaction and return to transfer state. Stop command is not required at the end of this type of multiple ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Write protect management Card data may be protected against either erase or write. The entire card may be permanently write protected by the manufacturer or content provider by setting the permanent or temporary write protect bits in the ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 ERASE: 1 Defines Forced Erase Operation (all other bits shall be ‘0’) and only the cmd byte is sent. LOCK/UNLOCK Locks the card Unlock the card (note that it is valid to set this ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Locking a card: Select a card (CMD7), if not previously selected already. Define the block length (CMD16), given by the 8 bit card lock/unlock mode, the 8 bit password size (in bytes), and the number of bytes of ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 State transition summary Table “Card State Transition Table” defines the card state transitions as a function of received command. Card State Transition Table Current state Command idle 1 CRC fail * Commands out of the supported class(es) class0 ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Current state Command idle class4 CMD16 CMD23 CMD24 CMD25 CMD26 CMD27 class5 CMD35 CMD36 CMD38 class6 CMD28 CMD29 CMD30 class7 CMD42 Notes: 1. “ ” means command is ignored, no state change and no response. Rev.0.02, Sep.15.2004, page ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Responses All responses are sent via command line (CMD), all data starts with the MSB. Format R1 (response command): response length 48 bits start bit card The contents of the status field are described in Chapter ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Status The response format R1 contains a 32-bit field with the name card status. This field is intended to transmit status information which is stored in a local status register of each card to the host. The following ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Status Bits Identifier Type Value 31 OUT_OF_RANGE ADDRESS_ERROR ‘0’= no error 29 BLOCK_LEN_ERRO ERASE_SEQ_ERR ERASE_PARAM WP_VIOLATION ‘0’= not ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Bits Identifier Type Value 16 CID_OVERWRITE ‘0’= no error CSD_OVERWRITE 15 WP_ERASE_SKIP CARD_ECC_ S X DISABLED 13 ERASE_RESET S R 12:9 CURRENT_STATE BUFFER_EMPTY S X 7:6 Reserved 5 APP_CMD ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Command Response Timings All timing diagrams use the following schematics and abbreviations: S: Start bit (= 0) T: Transmitter bit (Host = 1, Card = 0) P: One-cycle pull- End bit (= 1) Z: High ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 The host command and the card response are clocked out with the rising edge of the host clock. The delay between host command and card response is N for host command CMD3: Host command CMD S T content ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Last host command - next host command timing diagram After the last command, which does not force a response, has been sent, the host can continue sending the next command after at least N clock periods. CC Host ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Stream read The data transfer starts N clock cycles after the end bit of the host command. The bus transaction is AC identical to that of a read block command (refer to Figure “Data Read Timing”). As the ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Stream write The data transfer starts N clock cycles after the card response to the sequential write command was WR received. The bus transaction is identical to that of a write block command (see Figure “Timing of The ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Reset GO_IDLE_STATE (CMD0) is the software reset command, which sets the MultiMediaCard into the Idle State independently of the current state. In the Inactive State the MultiMediaCard is not affected by this command. After power-on the MultiMediaCard is ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 SPI Communication The SPI mode consists of a secondary communication protocol. This mode is a subset of the MultiMediaCard protocol, designed to communicate with a SPI channel, commonly found in Motorola’s (and lately a few other vendors’) microcontrollers. ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Bus Transfer Protection Every MultiMediaCard token transferred on the bus is protected by CRC bits. In SPI mode, the MultiMediaCard offers a non-protected mode which enables systems built with reliable data links to exclude the hardware or firmware ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 (READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks. Two types of multiple block read transactions are defined (the host can use either one at any time): Open-ended Multiple block read The number of blocks for the read multiple ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 from host to card Data in command Data out response After a data block has been received, the card will respond with a data-response token. If the data block has been received without errors, it will be programmed. ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 failure in the data-response token and ignore any further incoming data blocks. The host must than abort the operation by sending the ‘Stop Tran’ token. If the host uses partial blocks whose accumulated length is not block aligned ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Erase and Write Protect Management The erase and write protect management procedures in the SPI mode are identical to those of the MultiMediaCard mode. While the card is erasing or changing the write protection bits of the predefined ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Error Conditions Unlike the MultiMediaCard protocol, in the SPI mode the card will always respond to a command. The response indicates acceptance or rejection of the command. A command may be rejected not supported (illegal ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Commands and Arguments CMD index SPI mode Argument CMD0 Yes None CMD1 Yes None CMD2 No CMD3 No CMD4 No CMD5 Reserved CMD6 Reserved CMD7 No CMD8 Reserved CMD9 Yes None CMD10 Yes None CMD11 No CMD12 Yes ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 CMD index SPI mode Argument CMD24 Yes [31:0] data address CMD25 Yes [31:0] data address CMD26 No CMD27 Yes None CMD28 Yes [31:0] data address CMD29 Yes [31:0] data address CMD30 Yes [31:0] write protect data address CMD31 ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 CMD index SPI mode Argument CMD43... Reserved CMD54 CMD55 (Yes) [31:16] RCA [15:0] stuff bits CMD56 (Yes) [31:1] stuff bits [0:0] RD/WR* CMD57 Reserved CMD58 Yes None CMD59 Yes [31:1] stuff bits [0:0] CRC option CMD60 No Notes: ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Responses There are several types of response tokens the MultiMediaCard mode, all are transmitted MSB first: Format R1 This response token is sent by the card after every command with the exception of SEND_STATUS commands. It ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Format R2 This response token is two bytes long and sent as a response to the SEND_STATUS command. The format is given in Figure “R2 Response Format”. 1. Byte The first byte is identical ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Format R3 This response token is sent by the card when a READ_OCR command is received. The response length is 5 bytes (refer to Figure “R3 Response Format”). The structure of the first (MSB) byte is identical to ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Data Tokens Read and write commands have data transfers associated with them. Data is being transmitted or received via data tokens. All data bytes are transmitted MSB first. Data tokens are 4 to 2051 bytes long and have ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Clearing Status Bits As described in the previous paragraphs, in SPI mode, status bits are reported to the host in three different formats: response R1, response R2 and data error token (the same bits may exist in multiple ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Included Identifier in resp Type Illegal command Card ECC failed DataErr CC error DataErr Error DataErr WP erase skip Lock/Unlock ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 SPI Bus Timing All timing diagrams use the following schematics and abbreviations: H: Signal is high (logical ‘1’) L: Signal is low (logical ‘0’) X: Don’t care Z: High impedance state (-> Repeater Busy: Busy ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Card Response to Host Command Datain Dataout bytes response ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Reading The CSD Register Datain read command Dataout Single Block Write CS * ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Error Handling MultiMediaCards are defined as error free devices or as devices with a defined maximum bit error rate (with external error correction circuitry). To correct defects in the memory field of the cards the system may include ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Cyclic Redundancy Check (CRC) The CRC is intended for protecting MultiMediaCard commands, responses and data transfer against transmission errors on the MultiMediaCard bus. One CRC is generated for every command and checked for every response on the CMD ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Power Supply Power Supply Decoupling The and V lines supply the card with operating voltage. For this, decoupling capacitors for SS1 SS2 CC buffering current peak are used. These capacitors are placed on the bus ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Power on / off Each card has its own power on detection circuitry which puts the card into a defined state after the power- on. No explicit reset signal is necessary. The cards can also be reset by ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 3.6 V Bus master supply voltage 2.7 V 2.0 V Power up time Supply ramp up time Initialization sequence Initialization delay: The maximum of 1 msec, 74 clock cycles and supply ramp up time After power up (including ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Short Cut Protection The MultiMediaCards can be inserted/removed into/from the bus without damage. If one of the supply pins ( not connected properly, then the current is drawn through a data CC SS line ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Characteristics This chapter defines following characteristics: Temperature characteristics Electrical characteristics Temperature Characteristics Parameter Symbol Storage temperature Tstg Operating temperature Topr Junction temperature Tj Electrical Characteristics In this chapter the electrical characteristics for these Renesas MultiMediaCards are defined in ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Absolute Maximum Ratings Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Recommended Operating Conditions The recommended operating conditions define the parameter ranges for optimal performance and durability of these Renesas MultiMediaCards. Parameter Symbol Supply voltage V Inputs Low-level input voltage V High-level input voltage V Outputs High-level output I ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Operating Characteristics The operating characteristics are parameters measured in a MultiMediaCard system assuming the recommended operating conditions (refer to Chapter “Recommended Operating Conditions”). Parameter High speed supply 32 MByte current 64 MByte 128 MByte 256 MByte 512 MByte ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Clock Input Valid data Output : Invalid Timing Diagram of Data Input and Output The access time ( divided into two parts The synchronous access time. This time defines the time of the ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Access Time Parameter Synchronous access delay cycles Synchronous access delay Asynchronous access delay Memory access time Note: 1. Refer to Chapter “Read, Write and Erase Time-out Conditions”. In the CSD are two fields to code the asynchronous and ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Abbreviations and Terms Abbreviations Terms <n> Argument of a command or data field. CMD<n> MultiMediaCard bus command <n>. See Command. PP Push Pull, output driver type with low impedance driver capability for 0 and 1. OD Open Drain, ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Abbreviations Terms CIN Card individual number. CRC Cyclic redundancy check. ECC Error correction code. G(x) Generator polynomial of error correction/check code. TAC Asynchronous access delay NSAC Number of synchronous access cycles to be added to the access delay ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Precautionary Notes on Product Usage To ensure the correct usage of this product, the following precautionary notes must be strictly observed. Failure to follow these precautions could give rise to loss of data, product malfunction, or erroneous operation. ...
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... HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Physical Outline Full size HB28K032MM3 HB28L064MM3 HB28J128MM3 HB28J256MM3 HB28J512MM3 Front Back Rev.0.02, Sep.15.2004, page January, 2003 Tolerance: 0.1 mm 27.3 25.9 4.0 2.1 R02 Min. all around 3 R1.0 4.5 Min 1.2 Max R0.5 4.0 32.0 Unit: mm 0.2 ...
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HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3 Reduced size HB28K032RM3 HB28L064RM3 HB28J128RM3 HB28J256RM3 4.5 Min 1.2 Max ± 4 0.1 Rev.0.02, Sep.15.2004, page R0.2 Min all around 0.2 2 0.3 ´ ± 0.1 0.3 ´ 2 R0.5 C7 1.4 C6 ...
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... Feb.25.2004 Initial issue 0.02 Sep.15.2004 1 Description: Change of Notes2, addition of Notes3 12 R2W_FACTOR: Value (16) 12, 20 Addition of CONTENT_PROT_APP 33 In the figure: ‘looses’ to ‘loses’ the description of T HB28K032MM3/HB28K032RM3 HB28L064MM3/HB28L064RM3 HB28J128MM3/HB28J128RM3 HB28J256MM3/HB28J256RM3 HB28J512MM3 Data Sheet : ‘maximum’ to ‘typical’ AAD ...
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Sales Strategic Planning Div. Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble ...