saa4970t NXP Semiconductors, saa4970t Datasheet - Page 12

• Manufacturer Part Number: saa4970t
• Description: Economical Video Processing Ic Ecobendic
• Manufacturer: NXP Semiconductors

Philips Semiconductors
V
CNT_B is a 9-bit counter, which counts to up to 512 lines
per acquisition video field. The cycle length of the counter
is determined by either:
The counter value of CNT_B is monitored at the moment
the VI1 rising edge is detected and can be read out from
MUXB by the microcontroller. This value then indicates the
number of lines in a video field. If the window is closed,
without a VI1 rising edge having occurred during the
window, MUXB will also be filled with the momentary
contents of CNT_B.
If a write to ‘SAMPLE AQUI and DISPL’ is done, MUXB will
be loaded with the momentary CNT_B contents.
An interrupt can be generated on a pre-defined acquisition
line (Counter B-interrupt-Acquisition-b) by writing its line
number to the ‘set CB_intAb’ register. If the interrupt is not
desired, the register should be filled with a value above the
‘reset window’ register contents. The value 1FFH is
suggested. Otherwise the interrupt may be disabled by
bit 1 of the PLL control register (address 3D).
CNT_C is a 9-bit counter that resets to 0 at a pre-defined
state of CNT_B. The internal ‘Gate Enable’ signal is then
also set. ‘Gate Enable’ is reset at a pre-defined value of
CNT_C. At that moment also an interrupt can be
generated. If the interrupt is not desired, it can be disabled
by bit 3 in the PLL control register.
H
CNT_F is an 8-bit counter, which counts up to
256 positions per display video line. The cycle length of the
counter is determined by either:
For operation with the internal reset only, a value N in the
‘reset CNT_F’ register will result in an N + 1 length cycle.
The R2 input should now be kept HIGH or LOW. This
means in the ECOBENDIC the R2 output from the
ECO-PLL 3-state and the R2 signal will externally be kept
HIGH or LOW.
1996 Oct 25
ERTICAL ACQUISITION BLOCK
ORIZONTAL DISPLAY BLOCK
an external reset (rising edge of VI1) on every field or
an internal reset, generated at a certain value of the
counter itself, at the moment that the window is closed,
without a VI1 rising edge having occurred during the
window.
an external reset or a reset from the ECO-PLL (rising
edge of R2) on every line or
an internal reset, generated at a certain value of the
counter itself.
Economical video processing IC
(ECOBENDIC)
12
For operation with the external reset only, the ‘reset
CNT_F’ register must be loaded with a value above the
maximum line length. A value of FFH is suggested.
Whenever CNT_F is reset, the internal display horizontal
pulse HU is generated.
The signals BL, H2, KAD and internally GD (which
becomes RE in the gates block) have programmable sets
and resets, and can therefore have rising and falling edges
at any desired CNT_F value. If the set and reset registers
have equal contents, the signal will remain reset (reset
overruling set). To keep the signals set, the reset register
should remain above the maximum CNT_A value, while
the set value is within the CNT_A cycle range. The GD has
two pairs of set/reset registers, and can generate 4 edges
per line instead of 2. The KAD has three pairs of set/reset
registers, and can generate 6 edges per line instead of 2.
The GD pulse has a programmable fine shift of 0, 1, 2 or
3 CK2 pulses on both of its edges.
All the horizontal display output signals have enables on
the sets and resets. These enables will be effectively
changed only at the occurrence of the internal horizontal
HU pulse. Therefore it is possible to set up various signal
edges slowly by the microcontroller and effectuate them all
at once in a certain video line.
The VI2 input/output signal is monitored on its rising edge,
with regard to the CNT_F momentary value. By reading
out MUXD, the position of the edge becomes available for
the microcontroller. If VI2 is the video field pulse, the
position of the active edge within a video line becomes
available. This indicates the interlace situation of the
display video signal.
If a write to ‘SAMPLE AQUI and DISPL’ is done, MUXD will
be loaded with the momentary CNT_F contents.
If VI2 is used as an output, the ‘VHU register/comparator’
generates a line frequent pulse that is used in the vertical
display block for the timing of the VI2 edges within the
lines.
V
CNT_D is a 9-bit counter, which counts to maximum
512 lines per display video field. The cycle length of the
counter is determined by a reset action from the
microcontroller, i.e. writing to address 14H.
The counter value of CNT_D is monitored at the moment
the VI2 rising edge is detected and can be read out from
MUXE by the microcontroller. This value then indicates the
number of lines in a video field.
ERTICAL DISPLAY BLOCK
Preliminary specification
SAA4970T