saa4970t NXP Semiconductors, saa4970t Datasheet - Page 18

• Manufacturer Part Number: saa4970t
• Description: Economical Video Processing Ic Ecobendic
• Manufacturer: NXP Semiconductors

Philips Semiconductors
1996 Oct 25
Register 1FH (BL, H2 EN’s SR)
1FH
Registers 20H and 21H (PLL)
20H
21H
Register 22H (update HI pos)
22H
Register 23H (reset CNT_A)
23H
Register 24H (reset GI_intAa)
24H
REGISTER
Economical video processing IC
(ECOBENDIC)
0 to 7
0 to 7
0 to 7
BIT
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
enable set BL
enable reset BL
enable set H2
enable reset H2
PLL_CORE control
DIV123 control
VI1 synchronized
n
m
update HI pos
reset CNT_A
reset GI_intAa
NAME
enables rising edge of BL
enables falling edge of BL
enables rising edge of H2
enables falling edge of H2
not used
not used
not used
not used
if free-run mode (else don’t care):
PLL_div, bit 0; see Table 10
PLL_div, bit 1; see Table 10
0 (test bit)
MPIP processing; specifies dividing of CK1 and R1;
CK1
R1 = div
MPIP processing; specifies dividing of CK1 and R1;
CK1
R1 = div
R1 is synchronized by VI1 (= 1); no synchronisation (= 0)
coefficient n of PI filter (C
coefficient n of PI filter (C
coefficient n of PI filter (C
coefficient m of PI filter (C
coefficient m of PI filter (C
coefficient m of PI filter (C
coefficient m of PI filter (C
1
when register data = CNT_A then signal HI is set and CNT_B and
CNT_C are incremented
resets CNT_A when register data = CNT_A; generation of R1 output
signal, if en_R1_out = 1 and oe_CK1 = 0
resets Blanking-Acquisition-Interrupt
1 = free-run mode: not line-locked CK1/2 generation
0 = locked mode: CK1/CK2 generation is line-locked by Hs
1 = last frequency: generates last frequency in locked mode
0 = fixed frequency: CK1/CK2 rate is determined by PLL_div
PLL_CORE
PLL_CORE
18
16 kHz (RL1); bit 0; see Table 7
16 kHz (RL1); bit 1; see Table 7
=
=
1
1
2
2
CK2; CK1 = div
CK2; CK1 = div
p
p
p
i
i
i
i
= 2
= 2
= 2
= 2
= 2
= 2
= 2
FUNCTION
(n + 1)
(n + 1)
(n + 1)
(m + 2)
(m + 2)
(m + 2)
(m + 2)
), bit 0
), bit 1
), bit 2
CK1
CK1
), bit 0
), bit 1
), bit 2
), bit 3
PLL_CORE
PLL_CORE
Preliminary specification
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SAA4970T