gs8321e36agd-400i GSI Technology, gs8321e36agd-400i Datasheet

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gs8321e36agd-400i

Manufacturer Part Number
gs8321e36agd-400i
Description
2m X 18, 1m X 32, 1m X 36 36mb Sync Burst Srams
Manufacturer
GSI Technology
Datasheet
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline
• Dual Cycle Deselect (DCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 165-bump BGA package
• RoHs-compliant 165-bump BGA package available
Functional Description
Applications
The GS8321E18/32/36AD is a 37,748,736-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
Rev: 1.00a 2/2011
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
operation
Through
Pipeline
3-1-1-1
2-1-1-1
Flow
Curr
Curr
Curr
Curr
tCycle
tCycle
t
t
(x32/x36)
(x32/x36)
KQ
KQ
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
(x18)
(x18)
Parameter Synopsis
-400
355
440
245
310
2.5
2.5
4.0
4.0
1/32
-375
2.66
340
415
235
300
2.5
4.2
4.2
configured to count in either linear or interleave order with the
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS8321E18/32/36AD is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8321E18/32/36AD operates on a 3.3 V or 2.5 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
from the internal circuits and are 3.3 V and 2.5 V compatible.
GS8321E18/32/36AD-400/375/333/250/200/150
-333
335
385
225
285
2.5
3.3
4.5
4.5
-250
245
310
190
250
2.5
4.0
5.5
5.5
DDQ
-200
205
265
165
225
) pins are used to decouple output noise
3.0
5.0
6.5
6.5
-150
165
215
155
205
3.8
6.7
7.5
7.5
Unit
mA
mA
mA
mA
ns
ns
ns
ns
© 2010, GSI Technology
400 MHz–150 MHz
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
Preliminary
DD

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gs8321e36agd-400i Summary of contents

Page 1

... Preliminary 400 MHz–150 MHz 3.3 V I/O ) pins are used to decouple output noise DDQ -250 -200 -150 Unit 2.5 3.0 3.8 ns 4.0 5.0 6.7 ns 245 205 165 mA 310 265 215 mA 5.5 6.5 7.5 ns 5.5 6.5 7.5 ns 190 165 155 mA 250 225 205 mA © 2010, GSI Technology DD ...

Page 2

... DQPA C DDQ V NC DQA D DDQ V NC DQA E DDQ V NC DQA F DDQ V NC DQA G DDQ DQA NC J DDQ V DQA NC K DDQ V DQA NC L DDQ V DQA NC M DDQ DDQ © 2010, GSI Technology ...

Page 3

... DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ DDQ © 2010, GSI Technology ...

Page 4

... DQPB C DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ V NC DQPA N DDQ © 2010, GSI Technology ...

Page 5

... Linear Burst Order mode; active low Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect Low Core power supply I/O and Core Ground Output driver power supply No Connect 5/32 Preliminary I/Os; active low D © 2010, GSI Technology ...

Page 6

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321E18/32/36AD-400/375/333/250/200/150 GS8321E18/32/36AD Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 6/32 Preliminary A Memory Array – DQx1 DQx9 © 2010, GSI Technology ...

Page 7

... Note: The burst counter wraps to initial state on the 5th clock. 7/32 Preliminary Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: © 2010, GSI Technology ...

Page 8

... may be used in any combination with BW to write single or multiple bytes. D 8/32 Preliminary B B Notes and/ © 2010, GSI Technology ...

Page 9

... © 2010, GSI Technology 3 DQ High-Z High-Z High-Z High-Z High ...

Page 10

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321E18/32/36AD-400/375/333/250/200/150 Simplified State Diagram X Deselect First Write Burst Write 10/32 Preliminary First Read Burst Read BW, and GW) control inputs, and © 2010, GSI Technology ...

Page 11

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321E18/32/36AD-400/375/333/250/200/150 Simplified State Diagram with G X Deselect First Write Burst Write 11/32 Preliminary First Read Burst Read CR © 2010, GSI Technology ...

Page 12

... Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Min. Typ. Max. 3.0 3.3 3.6 2.3 2.5 2.7 3.0 3.3 3.6 2.3 2.5 2.7 Min. Typ. Max 0.3 2.0 — DD –0.3 — 0.8 © 2010, GSI Technology Unit Unit Unit V V ...

Page 13

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 13/32 Preliminary Typ. Max 0.3 — 0.3*V — DD Typ. Max 100 θ JA (C°/W) θ JB (C°/W) Airflow = 2 m/s TBD TBD 20% tKC © 2010, GSI Technology Unit V V Unit °C °C θ JC (C°/W) TBD ...

Page 14

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321E18/32/36AD-400/375/333/250/200/150 Symbol Test conditions I/O OUT Output Load 1 DQ 50Ω 30pF V DDQ/2 * Distributed Test Jig Capacitance 14/32 Preliminary Typ. Max. Unit Conditions V – DDQ Fig © 2010, GSI Technology pF pF ...

Page 15

... –8 mA, V OH3 OH DDQ 15/32 Preliminary Min Max – – –1 uA 100 uA IH –100 uA IL – – 2.375 V 1 3.135 V 2.4 V — 0.4 V © 2010, GSI Technology — — ...

Page 16

... Rev: 1.00a 2/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321E18/32/36AD-400/375/333/250/200/150 16/32 Preliminary © 2010, GSI Technology ...

Page 17

... GSI Technology -150 6.7 ns — — 3.8 ns 1.5 ns — 1.5 — ns 1.5 ns — 0.5 — ns 7.5 ns — — 7.5 ns 2.0 — ns 2.0 — ns 1.5 ns — 0.5 — ns 1.5 ns — ...

Page 18

... Pipeline Mode Timing (DCD) Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont tKL tKL tKH tKH tKC tKC ADSC initiated read and E3 only sampled with ADSC tS tKQ tOHZ tH tLZ Q(A) D(B) 18/32 Preliminary Deselect Deselect Deselected with E1 tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2010, GSI Technology tKQX ...

Page 19

... Flow Through Mode Timing (DCD) Deselect Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read masks ADSP E1 masks ADSP tH tS tOHZ tLZ Q(A) D(B) Q(C) 19/32 Preliminary Deselect tH Deselected with E1 tKQX tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2010, GSI Technology ...

Page 20

... Rev: 1.00a 2/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321E18/32/36AD-400/375/333/250/200/150 Sleep Mode Timing Diagram tKH tKH tKC tKC tKL tKL tZZS tZZH 20/32 Preliminary 2. The duration of SB tZZR © 2010, GSI Technology ...

Page 21

... RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Rev: 1.00a 2/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321E18/32/36AD-400/375/333/250/200/150 TDO should be left unconnected Description 21/32 Preliminary . The JTAG output DD © 2010, GSI Technology ...

Page 22

... JTAG TAP Block Diagram · · · · · · Boundary Scan Register 0 Bypass Register Instruction Register ID Code Register · · · · Control Signals Test Access Port (TAP) Controller 22/32 Preliminary · · TDO © 2010, GSI Technology ...

Page 23

... Rev: 1.00a 2/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321E18/32/36AD-400/375/333/250/200/150 Not Used 23/32 Preliminary GSI Technology JEDEC Vendor ID Code © 2010, GSI Technology 0 1 ...

Page 24

... JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 24/32 Preliminary 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2010, GSI Technology ...

Page 25

... Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.00a 2/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321E18/32/36AD-400/375/333/250/200/150 Description 25/32 Preliminary Notes © 2010, GSI Technology ...

Page 26

... V 0.4 V — – 100 mV V — DDQ — 100 mV V JTAG Port AC Test Load DQ 50Ω 30pF V /2 DDQ * Distributed Test Jig Capacitance © 2010, GSI Technology ...

Page 27

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321E18/32/36AD-400/375/333/250/200/150 tTKC tTKC tTKH tTKH tTH tTS tTH tTS tTKQ tTH tTS Min Max Unit — — — ns — — ns — 27/32 Preliminary tTKL tTKL © 2010, GSI Technology ...

Page 28

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321E18/32/36AD-400/375/333/250/200/150 BOTTOM VIEW Ø0. Ø0. Ø0.40~0.60 (165x 1.0 10.0 13±0.05 B 0.20(4x) 28/32 Preliminary A1 CORNER 1.0 © 2010, GSI Technology ...

Page 29

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00a 2/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 30

... GS8321E32AGD-200 GS8321E32AGD-150 GS8321E36AGD-400 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8321E18AD-200IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 31

... GS8321E32AGD-400I GS8321E32AGD-375I GS8321E32AGD-333I GS8321E32AGD-300I GS8321E32AGD-250I GS8321E32AGD-200I GS8321E32AGD-150I GS8321E36AGD-400I GS8321E36AGD-375I GS8321E36AGD-333I GS8321E36AGD-300I GS8321E36AGD-250I GS8321E36AGD-200I GS8321E36AGD-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8321E18AD-200IT. ...

Page 32

... Sync SRAM Datasheet Revision History Types of Changes File Name Format or Content 8321ExxA_r1 Rev: 1.00a 2/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321E18/32/36AD-400/375/333/250/200/150 Page;Revisions;Reason • Creation of new datasheet 32/32 Preliminary © 2010, GSI Technology ...

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