at78c5009 ATMEL Corporation, at78c5009 Datasheet

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at78c5009

Manufacturer Part Number
at78c5009
Description
Serial Ata Host Bridge
Manufacturer
ATMEL Corporation
Datasheet
Features
Overview
The AT78C5009 SATA Controller bridges the conventional Parallel ATA devices with
Serial ATA PHY transceivers. It includes a Serial ATA Link layer, a Transport layer, a
Command Layer, two 256 x 32 FIFOs and an IDE Host/Target Controller, a Serial ATA
Core and an IDE Controller, and is fully compliant with Serial ATA Gen1. The PHY
block is connected to the ATA block by a 20-bit transmit and a 20-bit receive data bus.
This host bridge is intended to adapt a Serial ATA Device interface to an Ultra ATA100
Host interface. Ultra DMA is a data transfer protocol used with the READ DMA,
WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED, and PACKET
commands.
Operates as Host Bridge Between Serial ATA and Parallel ATA interfaces
Ultra ATA100 Mode Supported with Rates up to 100 MB/s
Data is Transferred on Both Edges of the STROBE when in Ultra DMA Mode
16-bit CRC is Calculated on a Per-burst Basis
Ultra DMA5 Compliant Drive Interfaces
Compatible with 48-bit LBA Methods of Addressing
Dual 1024-byte Transmit/Receive FIFO for Overrun Prevention
8B/10B Encoding and Decoding in Serial ATA Link Layer
Low Power: < 380 mW
Supports PIO Modes 0, 1, 2, 3 and 4
Supports UDMA Modes 0, 1, 2, 3, 4, and 5
Supports 80-conductor Cable for UDMA Modes 4, and 5
Note: This is a summary document. A complete document
is available under NDA. For more information, please con-
tact your local Atmel sales office.
Serial ATA Host
Bridge
AT78C5009
Summary
3511AS–NETST–8/04

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at78c5009 Summary of contents

Page 1

... Supports 80-conductor Cable for UDMA Modes 4, and 5 Overview The AT78C5009 SATA Controller bridges the conventional Parallel ATA devices with Serial ATA PHY transceivers. It includes a Serial ATA Link layer, a Transport layer, a Command Layer, two 256 x 32 FIFOs and an IDE Host/Target Controller, a Serial ATA Core and an IDE Controller, and is fully compliant with Serial ATA Gen1 ...

Page 2

... Figure 1. AT78C5009 Block/PAD Interconnect Rx[19:0], Receive Data Bus RX+ Tx[19:0], Transmit Data Bus RX- TBC (transmit byte clock 75 MHz) RX+ RX- RBC (receive byte clock 75 MHZ) 1.5Gb/s Transceiver AT78C5009 2 TX_ENABLE COMMA_DETECT REALIGN COMWAKE COMRI PARTIAL SLUMBER ATA/Serial ATA STOP Controler RESET RX_LOCKED RX_ERROR SCLK SDEN SDATA ...

Page 3

... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...

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