peel18cv8ti-25 ETC-unknow, peel18cv8ti-25 Datasheet

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peel18cv8ti-25

Manufacturer Part Number
peel18cv8ti-25
Description
Cmos Programmable Electrically Erasable Logic Device
Manufacturer
ETC-unknow
Datasheet
Features
General Description
The PEEL18CV8 is a Programmable Electrically Erasable
Logic (PEEL) device providing an attractive alternative to
ordinary PLDs. The PEEL18CV8 offers the performance,
flexibility, ease of design and production practicality needed
by logic designers today.
The PEEL18CV8 is available in 20-pin DIP, PLCC, SOIC
and TSSOP packages with speeds ranging from 5ns to
25ns with power consumption as low as 37mA. EE-Repro-
grammability provides the convenience of instant repro-
gramming for development and reusable production
inventory minimizing the impact of programming changes
or errors. EE-Reprogrammability also improves factory
testability, thus assuring the highest quality possible.
Figure 1 Pin Configuration
Multiple Speed Power, Temperature Options
CMOS Electrically Erasable Technology
Development / Programmer Support
- V
- Speeds ranging from 5ns to 25 ns
- Power as low as 37mA at 25MHz
- Commercial and industrial versions available
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
- Third party software and programmers
- ICT PLACE Development Software and PDS-3
- PLD-to-PEEL JEDEC file translator
programmer
CC
DIP
PLCC
®
= 5 Volts ±10%
Technology
CMOS
International
CMOS Programmable Electrically Erasable Logic Device
I/CLK
TSSOP
GND
SOIC
I
I
I
I
I
I
I
I
PEEL™ 18CV8 -5/-7/-10/-15/-25
10
2
3
4
5
6
7
8
9
1
20
19
18
17
16
15
14
13
12
11
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
1
Architectural Flexibility
The PEEL18CV8 architecture allows it to replace over 20
standard 20-pin PLDs (PAL, GAL, EPLD etc.). It also pro-
vides additional architecture features so more logic can be
put into every design. ICT’s JEDEC file translator instantly
converts to the PEEL18CV8 existing 20-pin PLDs without
the need to rework the existing design. Development and
programming support for the PEEL18CV8 is provided by
popular third-party programmers and development software.
ICT also offers free PLACE development software and a
low-cost development system (PDS-3).
Figure 2 Block Diagram
Application Versatility
- Enhanced architecture fits in more logic
- 74 product terms x 36 input AND array
- 10 inputs and 8 I/O pins
- 12 possible macrocell configurations
- Asynchronous clear
- Independent output enables
-- 20 Pin DIP/SOIC/TSSOP and PLCC
- Replaces random logic
- Super sets PLDs (PAL, GAL, EPLD)
- Enhanced Architecture fits more logic than ordinary
PLDs
Commercial/
Industrial
04-02-004H

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peel18cv8ti-25 Summary of contents

Page 1

International CMOS Technology PEEL™ 18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features Multiple Speed Power, Temperature Options - Volts ±10 Speeds ranging from 5ns Power as low as 37mA ...

Page 2

International CMOS Technology Figure 3 PEEL18CV8 Logic Array Diagram 2 PEEL TM 18CV8 04-02-004H ...

Page 3

International CMOS Technology Function Description The PEEL18CV8 implements logic functions as sum-of- products expressions in a programmable-AND/fixed-OR logic array. User-defined functions are created by program- ming the connections of input signals into the array. User- configurable output structures in ...

Page 4

International CMOS Technology function as a dedicated input, a dedicated output bi- directional I/O. Opening every connection on the output enable term will permanently enable the output buffer and yield a dedicated output. Conversely, if every connection ...

Page 5

International CMOS Technology Figure 5 Equivalent Circuits for the Twelve Configurations of the PEEL18CV8 I/O Macrocell Configuration Input/Feedback Select # Bi-directional I Bi-directional I/O 3 ...

Page 6

International CMOS Technology Absolute Maximum Ratings Symbol Parameter V Supply Voltage Voltage Applied to Any Pin I Output Current O T Storage Temperature ST T Lead Temperature LT Operating Range Symbol Parameter Vcc ...

Page 7

International CMOS Technology A.C. Electrical Characteristics 8 Over the operating range Symbol Parameter Input to non-registered output Input to output enable Input to output disable t Clock to ...

Page 8

... PEEL18CV8S-7 PEEL18CV8P-10 PEEL18CV8PI-10 PEEL18CV8J-10 PEEL18CV8JI-10 PEEL18CV8S-10 PEEL18CV8SI-10 PEEL18CV8T-10 PEEL18CV8TI-10 PEEL18CV8P-15 PEEL18CV8PI-15 PEEL18CV8J-15 PEEL18CV8JI-15 PEEL18CV8S-15 PEEL18CV8SI-15 PEEL18CV8T-15 PEEL18CV8TI-15 PEEL18CV8P-25 PEEL18CV8PI-25 PEEL18CV8J-25 PEEL18CV8JI-25 PEEL18CV8S-25 PEEL18CV8SI-25 PEEL18CV8T-25 PEEL18CV8TI-25 Thevenin V L Equivalent R L Output 480k 480k 228k 235 159 95 159 118 68 Speed ...

Page 9

International CMOS Technology Part Number Package P = 20-pin Plastic 300mil DIP J = 20-pin Plastic (J) Leaded Chip Carrier (PLCC 20-pin SOIC 300 mil Gullwing T = 20-pin TSSOP 170 mil Device Suffix PEEL18CV8 PI-25 Speed ...

Page 10

International CMOS Technology 10 PEEL TM 18CV8 04-02-004H ...

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