lis3dsh STMicroelectronics, lis3dsh Datasheet - Page 23

• Manufacturer Part Number: lis3dsh
• Description: Mems Digital Output Motion Sensor Ultra Low-power High Performance Three-axis “nano” Accelerometer
• Manufacturer: STMicroelectronics

LIS3DSH
6.1.1
I
The transaction on the bus is started through a start (ST) signal. A start condition is defined
as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has
been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.
The slave address (SAD) associated to the LIS3DSH is 00111xxb whereas the xx bits are
modified by the SEL/SDO pin in order to modify the device address. If the SEL pin is
connected to the voltage supply, the address is 0011101b, otherwise the address is
0011110b if the SEL pin is connected to ground. This solution permits to connect and
address two different accelerometers to the same I
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the
7 LSb represents the actual register address while the ADD_INC bit (CTRL_REG6) defines
the address increment.
The slave address is completed with a read/write bit. If the bit is ‘1’ (Read), a repeated start
(SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write), the
master transmits to the slave with direction unchanged.
SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Table 11.
Table 12.
2
C operation
Master
Command
Slave
2
Read
Write
Read
Write
C embedded inside the LIS3DSH behaves as a slave device and the following
SAD+Read/Write patterns
Transfer when master is writing one byte to slave
ST
SAD[6:2]
00111
00111
00111
00111
SAD + W
Doc ID 022405 Rev 1
SAD[1] = SEL
1
1
0
0
SAK
SUB
SAD[0] = SEL
2
C lines.
0
1
0
1
SAK
Table 11
explains how the
DATA
R/W
1
0
1
0
Digital interfaces
00111101
00111100
00111011
00111010
SAK
SAD+R/W
SP
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