wpcn385l Winbond Electronics Corp America, wpcn385l Datasheet - Page 2

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wpcn385l

Manufacturer Part Number
wpcn385l
Description
Lpc-to-lpc Switch, Fast Infrared Port, Serial Port And Gpios
Manufacturer
Winbond Electronics Corp America
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
wpcn385lAODG
Manufacturer:
TEXAS
Quantity:
5
www.winbond.com
Features
Internal Block Diagram
— Hot plugability
— LPCPD and CLKRUN support
— The connection is controlled by software
— Low switch resistance and propagation delay
— Programmable Clock to Reset Delay
Fast Infrared Port (FIR)
— Software compatible with the 16550A and the 16450
— Shadow register support for write-only bit monitoring
— FIR IrDA 1.1 compliant
— HP-SIR
— ASK-IR option of SHARP-IR
— DASK-IR option of SHARP-IR
— Consumer Remote Control supports RC-5, RC-6,
— DMA support: one or two channels
Serial Port (SP)
— Software compatible with the 16550A and the 16450
— Shadow register support for write-only bit monitoring
— UART data rates up to 1.5 Mbaud
18 General-Purpose I/O (GPIO) Ports
— Supports IRQ assertion
— Programmable drive type for each output pin (open-
— Programmable option for internal pull-up resistor on
— Output lock option
— Input debounce mechanism
Docking LPC Switch
NEC, RCA and RECS 80
drain, push-pull or output disable)
each input pin
14.31818 MHz
Generator
48 MHz
Clock
GPIO Ports
Ports
I/O
Serial Port
Interface
Serial
2
Interface
Interface
LPC System Interface
— 8-bit I/O cycles
— LPCPD and CLKRUN support
— Implements PCI mobile design guide recommenda-
PC2001 and ACPI 3.0 Compliant
— PnP Configuration Register structure
— Flexible resource allocation for all logical devices
Clock Sources
— 14.318 MHz or 48 MHz clock input
— LPC clock, 0 or 30 MHz to 33 MHz
— 14.318 MHz or 48 MHz clock output to the docking
Strap Configuration
— Base Address (BADDR) strap to determine the base
— Docking LPC disable (DLPC_DIS) strap to control
— Strap Inputs to select testability mode
Power Supply
— 3.3V supply operation
— All pins are 5V tolerant, except LPC bus pins
— All pins are back-drive protected, except LPC bus pins
Testability
— XOR Tree
— TRI-STATE device pins
FIR Port
Bus
FIR
tion (PCI Mobile Design Guide 1.1, Dec. 18, 1998)
station
address of the Index-Data register pair
the LPC-to-LPC Switch
LPC Interface
Relocatable base address
15 IRQ routing options
Optional 8-bit DMA channels (where applicable)
selected from four possible DMA channels
LPC Switch
Docking
Docking LPC
Interface
Revision 1.0

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