w66910 Winbond Electronics Corp America, w66910 Datasheet
w66910
Related parts for w66910
w66910 Summary of contents
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... TE Mode ISDN S/T-Controller with Microprocessor W66910 PCI ISDN S/T-Controller W66910 Interface Data Sheet -1 - Publication Release Date: Data Sheet Feb,2001 Revision 1.0 ...
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... The information described in this document is the exclusive intellectual property of Winbond Electronics Corp and shall not be reproduced without permission from Winbond. Winbond is providing this document only for reference purposes for W66910-based system design. Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice ...
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... GCI ODE ERIAL NTERFACE 7.8.1 GCI Mode C/I0 Channel Handling ............................................................................................................................ 39 7.8.2 GCI Mode Monitor Channel Handling....................................................................................................................... 39 7 BIT ICROPROSESSOR NTERFACE 7. ..................................................................................................................................................... 40 ERIPHERAL ONTROL 8. REGISTER DESCRIPTIONS ............................................................................................................................................. 42 ................................................................................................................................... 16 ...................................................................................................................................... 33 ...................................................................................................................................... 36 ....................................................................................................................... 36 .................................................................................................................................... ...................................................................................................................... 40 IRCUIT -3 - Data Sheet W66910 PCI ISDN S/T-Controller Publication Release Date: Revision 1.0 Feb,2001 ...
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... B1_XFIFO Write Address 21H ............................................................................................... 65 8.2.3 B1_ch command register B1_CMDR Read/Write Address 22H ................................................................................. 66 8.2.4 B1_ch Mode Register B1_MODE Read/Write Address 23H ..................................................................................... 67 8.2.5 B1_ch Extended Interrupt Register B1_EXIR Read_clear Address 24H .................................................................. 68 ................................................................................................................. 42 D_SAM Read/Write Address 0BH............................................................................. Data Sheet W66910 PCI ISDN S/T-Controller Publication Release Date: Revision 1.0 Feb,2001 ...
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... BSOLUTE AXIMUM ATING 9 .................................................................................................................................................................. 73 OWER UPPLY 9 ....................................................................................................................................................... 73 HARACTERISTICS 9 RELIMINARY WITCHING HARACTERISTICS 9.4.1 PCM Interface Timing ............................................................................................................................................... 75 9.4.2 8-bit Microprocessor Timing...................................................................................................................................... 76 9 ........................................................................................................................................... 78 IMING EST ONDITIONS 10. ORDERING INFORMATION .......................................................................................................................................... 79 11. PACKAGE SPECIFICATIONS ........................................................................................................................................ 80 W66910 PCI ISDN S/T-Controller ..................................................................................................................... Data Sheet Publication Release Date: Feb,2001 Revision 1.0 ...
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... LIST OF FIGURES FIG.3.1 W66910 PIN CONFIGURATION - INTEL BUS MODE..................................................................................................9 FIG.3.2 W66910 PIN CONFIGURATION - MOTOROLA BUS MODE .....................................................................................10 FIG.5.1 W66910 INTERFACE CIRCUIT FOR ISDN EMBEDED APPLICATION ....................................................................13 FIG.6.1 W66910 FUNCTIONAL BLOCK DIAGRAM ...............................................................................................................14 FIG.7.1 FRAME STRUCTURE AT S/T INTERFACE................................................................................................................17 FIG.7.2 W66910 WIRING CONFIGURATION IN TE APPLICATIONS....................................................................................18 FIG.7.3 EXTERNAL TRANSMITTER CIRCUITRY..................................................................................................................19 FIG ...
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... LIST OF TABLES TABLE 4.1 W66910 PIN DESCRIPTIONS ................................................................................................................................11 TABLE 7.1 OUTPUT PHASE DELAY COMPENSATION TABLE...........................................................................................20 TABLE 7.2 LAYER 1 COMMAND CODES ..............................................................................................................................22 TABLE 7.3 LAYER 1 INDICATION CODES ............................................................................................................................22 TABLE 7.4 D PRIORITY CLASSES ..........................................................................................................................................26 TABLE 7.5 D PRIORITY COMMANDS/INDICATIONS ..........................................................................................................26 TABLE 7.6 MULTIFRAME STRUCTURE IN S/T INTERFACE ...............................................................................................29 TABLE 8.1 REGISTER ADDRESS MAP: CHIP CONTROL AND D CHANNEL HDLC ..........................................................42 TABLE 8.2 REGISTER SUMMARY: CHIP CONTROL AND D CHANNEL HDLC ..................................................................43 TABLE 8 ...
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... GENERAL DESCRIPTION The Winbond's single chip TE mode ISDN S/T interface controller (W66910 all-in-one device suitable for ISDN Internet access. Three HDLC controllers are incorporated in the chip, one for D channel and the other two for B channels. These HDLC controllers facilitate efficient access to signaling and data services. It also provides 8-bit microprocessor interface to serve as general purposed controller for embedded applications ...
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... PIN CONFIGURATION RST# 81 VSSD 82 VDDD 83 84 CLK VSSB 88 89 VDDB 100 FIG.3.1 W66910 PIN CONFIGURATION - INTEL BUS MODE ...
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... FIG.3.2 W66910 PIN CONFIGURATION - MOTOROLA BUS MODE W66910 PCI ISDN S/ ...
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... O PCM bit synchronization clock of 1.536 MHz. O PCM transmit data output. A maximum of two channels with 64 Kbit/s data rate can be multiplexed on this signal. I PCM receive data input. A maximum of two channels with 64 Kbit/s 11 Data Sheet W66910 PCI ISDN S/T Controller te: Revision 1.0 ...
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... VDDD 17,58,67,83 VDDA 51 VDDB 6,32,43,89 VSSD 16,59,68,82 VSSA 48 VSSB 5,31,42,88 W66910 PCI ISDN S/T-Controller data rate can be multiplexed on this signal. Needs external pull-up. ISDN Signals and External Crystal I S/T bus receiver input (negative). I S/T bus receiver input (positive). O S/T bus transmitter output (positive). O S/T bus transmitter output (negative). I Crystal or Oscillator clock input. The clock frequency: 7 ...
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... ISDN TA, Router or other embedded application The all-in-one characteristic of W66910 makes it excellent for ISDN embeded application. W66910 integrates three HDLC controllers in the chip and interfaces to 8-bit microprocessor bus directly. In addition, W66910 provides peripheral control circuits for PCM CODEC and POTS interface. ...
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... BLOCK DIAGRAM The block diagram of W66910 is shown in Figure 6.1 4-wire S/T GCI Bus Crystal/Oscillator (7.68 MHz) POTS circuit FIG.6.1 W66910 FUNCTIONAL BLOCK DIAGRAM B2 2B+D B1 Line Serial Transceiver Interface & Bus D AMI/BIN (SIB) B-channel Switching Conversion D 2B+D B1 HDLC HDLC GCI Controller Controller Circuit FIFO FIFO ...
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... FUNCTIONAL DESCRIPTIONS 7.1 Main Block Functions The functional block diagram of W66910 is shown in Fig.6.1. The main function blocks are : - Layer 1 function according to ITU-T I.430 - Serial Interface Bus (SIB channel switching - GCI bus interface - PCM port (x 2) and internal B channel switching - D channel HDLC controller ...
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... The frame begin is marked by a framing bit, which is followed balancing bit. The first binary "0" following the framing bit balancing bit is of the same polarity as the framing bit balancing bit, and subsequent binary zeros must alternate in polarity. W66910 PCI ISDN S/T-Controller -16 - ...
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... N = Bit set to a binary value N= NOT Bit within B channel Bit within B channel Bit used for activation S = Bit used for S channel M = Multiframe bit -17 - Data Sheet W66910 PCI ISDN S/T-Controller ...
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... W66910 TR TE (a) Point-to-point configuration TR W66910 TE1 (b) Short passive bus configuration 50m TR W66910 . . . . . TE1 (c) Extended passive bus configuration FIG.7.2 W66910 WIRING CONFIGURATION IN TE APPLICATIONS W66910 PCI ISDN S/T-Controller 1000 m 100~200 m TR 10m W66910 . . . . . TE8 100~200 m 10m W66910 TE8 -18 - Publication Release Date: ...
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... SR1 SR2 FIG.7.4 EXTERNAL RECEIVER CIRCUITRY termination is 750 mV, zero to peak. Transformers with 2:1 turn ration are needed at resistors protect the device inputs, while the 10 k VDD 1.8k 8.2k GND VDD 1.8k 8.2k -19 - Data Sheet W66910 PCI ISDN S/T-Controller 2:1 100 2:1 100 Publication Release Date: Revision 1.0 resistors Feb,2001 ...
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... W66910 does not need RC filter on receiver side, therefore zero delay compensation is selected normally. This is also the default setting. The PCM output clocks (PFCK1-2, PBCK) are locked to the S-interface timing with jitter. See the electrical specification. 7.2.3 Layer 1 Activation/Deactivation The layer 1 activation/deactivation procedures are implemented by a finite state machine according to I.430 TE mode. The state transitions are triggered by signals received at S interface or commands issued from microprocessor ...
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... INFO 0 has been received on S interface before expiration of T3. F5 Identifying Input After the receipt of any non-INFO 0 signal from NT, the W66910 ceases to transmit INFO 1 and awaits identification of INFO 2 or INFO 4. This state is reached at most 50 s after a signal different from INFO 0 is present at the receiver of the S interface. ...
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... For example, at "F3 Deactivated with clock" state, the layer 1 will stay at this state if the command is "ECK" and the INFO 0 is received on S interface. At this state, it provides "CE" indication to the microprocessor and transmits INFO interface. The "AR8/10" command causes transition to F4 and non-INFO 0 signal causes transition to W66910 PCI ISDN S/T-Controller Code Description ...
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... F5. Note that the command code writtern by the microprocessor in CIX register and indication code written by layer 1 in CIR register are transmitted repeatedly until a new code is written. W66910 PCI ISDN S/T-Controller -23 - Publication Release Date: Data Sheet Feb,2001 Revision 1.0 ...
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... FIG.7.5 LAYER 1 ACTIVATION/DEACTIVATION STATE DIAGRAM - NORMAL MODE W66910 PCI ISDN S/T-Controller DRC ECK AR8/10 3) ^i0 ...
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... RST can be issued at any state, while SCP, SCZ and EAL can be issued only F7 one of the commands : ECK, DRC, RST. 3. Continuous pulses at 96 kHz. 4. Isolated pulses at 2 kHz. 5. The INFO 3 is transmitted internally only. FIG.7.6 LAYER 1 ACTIVATION/DEACTIVATION STATE DIAGRAM - SPECIAL MODE W66910 PCI ISDN S/T-Controller EAL None ...
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... Indication Abbr. Activate indication with priority 8 AI8 Activate indication with priority 10 AI10 7.2.5 Frame Alignment The following sections describe the behavior of W66910 in respect to the CTS-2 conformance test procedures for frame alignment. Please refer to ETSI-TM3 Appendix B1 for detailed descriptions. Lower level 9 11 Remarks ...
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... This is to test the number k of IX_96 kHz frames necessary for loss of frame alignment. Device Settings W66910 k =2 7.2.5.5 FAinfB_kfr This is to test the number k of IX_I4noflag frames necessary for loss of frame alignment. W66910 PCI ISDN S/T-Controller Result Pass Result Pass bit (F ="1") in the transmitted frame. ...
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... Settings W66910 7.2.5.7 Faregain This is to test the number m of good frames necessary for regain of frame alignment. The TE regains frame alignment at m+1 frame. The W66910 achieves synchronization after 5 frames, i.e m=4. Device Settings W66910 7.2.6 Multiframe Synchronization As specified by ITU-T I.430, the Q bit is transmitted from the position normally occupied by the auxiliary framing bit ( one frame out of 5, whereas the S bit is transmitted from ...
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... ONE 12 ZERO 13 ZERO 14 ZERO 15 ZERO 16 ONE 17 ZERO 18 ZERO 19 ZERO 20 ZERO 1 ONE 2 ZERO etc. 7.2.7 Test Functions The W66910 provides loop and test functions as follows: NT-to-TE NT-to-TE TE-to-NT M bit S bit F -bit position A ONE S1 ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO S2 ZERO ZERO ZERO ZERO ...
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... S bus timing. This loop function is used for test of PCM and higher layer functions, excluding layer 1. After hardware reset, W66910 will power down if S bus is not connected or if there is no signal on the S bus. In this case, the C/I command ECK must be issued to power up the chip. ...
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... The multiplexing/demultiplexing functions are carried out in the Serial Interface Bus (SIB) block. In addition, the B1 and B2 channels can be individually set to carry 64 kbps or 56 kbps traffic. 7.4 B Channel Switching There are three switching terminals in W66910: layer 1, layer 2, CODEC interface. Layer 1 can be S CODEC interface can be PCM port or GCI bus. They are set in in GCR register. GMODE GACT Layer 1 ...
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... B1_SW[1: order to receive PCM2/GCI_B2. Secondly look at PCM2/GCI_B2 receive table, we find that, to receive L1_B1, there are two combinations of PXC, B1_SW[1:0] : 100 or 101. The logical AND result of these two tables is PXC=1, B1_SW[1:0]=01. This is the value which must be programmed in the registers. W66910 PCI ISDN S/T-Controller Layer2-B1 Receive Table B1_SW[1:0] ...
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... PCM Port There are two PCM ports in W66910. Data is transmitted/ received when PFCK1/PFCK2 is HIGH. The frame synchronization clocks (PFCK1-2) are 8 kHz and the bit synchronization clock (PBCK) is 1.536 MHz. 7.6 D Channel HDLC Controller There are two HDLC protocols that are used for ISDN layer 2 functions : LAPD and LAPB. Their frame formats are shown below ...
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... Note. The LAPD protocol uses the CRC_ITU-T for Frame Check Sequence. The polynominal is X For address recognition, the W66910 provides four programmable registers for individual SAPI and TEI values, SAP1-2 and TEI1-2, plus two fixed values for group SAPI and TEI, SAPG and TEIG. The SAPG equals 02H(C/R=1) or 00H(C/R=0) which corresponds to SAPI = 0 ...
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... If the microprocessor fails to respond the D_XFR interrupt within a given time (32 ms), a data underrun condition will occur. The W66910 will automatically reset the transmitter and send inter frame time fill pattern (all 1' channel. The microprocessor is informed about this condition via an XDUN (Transmit Data Underrun) interrupt in D_EXIR register. The microprocessor must wait until transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data ...
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... Transparent mode: The received frame address is compared with the contents in receive address registers. In addition, the comparisons can be selectively masked bit-by-bit via address mask registers. Comparison is disabled when the corresponding mask bit is "1". W66910 PCI ISDN S/T-Controller -36 - Publication Release Date: ...
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... The microprocessor indicates the end of the frame transmission by issuing XME (Transmit Message End) and XMS commands at the same time. The transmitter then transmits all the data left in the transmit FIFO and appends the CRC and closing flag. After this, a XFR interrupt is generated. W66910 PCI ISDN S/T-Controller -37 - Publication Release Date: ...
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... FIFO threshold is 64 and the B channel data rate is 64 kbps. If the microprocessor fails to respond within the given reaction time, the transmit FIFO will hold no data to transmit. In this case, the W66910 will automatically reset the transmitter and send idle channel pattern defined in Bn_IDLE register. The microprocessor is informed about this via a Transmit Data Underrun interrupt (XDUN bit in Bn_EXIR register) ...
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... In the transmit direction, the code written in CIX is continuously transmitted in the channel. 7.8.2 GCI Mode Monitor Channel Handling The Monitor channel protocol is a handshake protocol used for high speed information exchange between the W66910 and other devices. The Monitor channel is necessary for: Programming and controlling devices attached to the GCI interface. ...
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... The microprocessor may either enforce a 1 (idle state setting the control bit MRC or MXC (MOCR register enable the control of these bits internally by the W66910 according to the Monitor channel protocol. Thus, before a data exchange can begin, the control bit MRC, or MXC should be set the microprocessor. ...
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... W66910, therefore reduce the IO requirement of microprocessor. The peripheral control function includes timer, interrupt inputs and programmable IO. There are two timers implemented in W66910: TIMR1 and TIMR2. TIMR1 is a long period timer whcich can be used to control the cadence of ring tone. TIMR2 is a short period timer which can be used to generate the 20 Hz ring signal. ...
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... PCTL 8.1. MO0R 8.1.29 1C R/W MO0X 8.1.30 1D R_clear MO0I 8.1.31 1E R/W MO0C W66910 PCI ISDN S/T-Controller Description D channel receive FIFO D channel transmit FIFO D channel command register D channel mode control Timer 1 Interrupt status register Interrupt mask register D channel extended interrupt D channel extended interrupt mask D channel transmit status ...
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... TA23 VN0 LOV RBC12 RBC11 RBC6 RBC5 RBC4 RBC3 TIDLE TCN5 TCN4 TCN3 RC3 0 SRST 0 -43 - Data Sheet W66910 PCI ISDN S/T-Controller XME XRST MFD DLP RLP CNT2 CNT1 CNT0 D_EXI B1_EXI B2_EXI D_EXI B1_EXI B2_EXI ISC T1EXP ...
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... CI1R_6 CI1R_5 CI1R_4 0 CI1X_6 CI1X_5 CI1X_4 0 0 MO1C MO0C 1 1 MO1C D_RFIFO Read Address 00H D_XFIFO Write Address 01H -44 - Data Sheet W66910 PCI ISDN S/T-Controller CODR2 CODR1 CODR0 CODX2 CODX1 CODX0 OE0 0 PXC MER0 MDA0 MAB0 ...
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... This command also results in a transmit FIFO ready condition. Writing “0” to this bit has no effect. 8.1.4 D_ch Mode Register D_MODE Value after reset : 00H RACT XACTB 0 RACT Receiver Active W66910 PCI ISDN S/T-Controller D_CMDR Write Address 02H XMS 0 XME XRST ...
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... Single mode: The timer counts once and generates a T1EXP interrupt when expires Periodical mode: The timer counts periodically and generates an interrupt at each expiration. CNT6-0 Count Value The expiration time is defined as CNT[6:0] * 0.1 second W66910 PCI ISDN S/T-Controller Read/Write Address 04H ...
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... This bit indicates that at least one interrupt bit has been set in B1_EXIR register. ISTA Read_clear XINT1 XINT0 D_EXI B1_EXI -47 - Data Sheet W66910 PCI ISDN S/T-Controller Address 05H 1 0 B2_EXI 64 bytes has been received. The whole frame Publication Release Date: Revision 1.0 Feb,2001 ...
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... XDUN Transmit Data Underrun This interrupt indicates the D_XFIFO has run out of data. In this case, the W66910 will automatically reset the transmitter and send the inter frame time fill pattern (all 1' channel. The microprocessor must wait until transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data ...
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... The layer 1 D channel is not ready. No transmission is allowed. 1: The layer 1 D channel is ready. Layer 2 can transmit data to layer 1. Note : Due to design mistake, DRDY=1 does not mean S/T layer state. Software has to check “DRDY=1 and C/I W66910 PCI ISDN S/T-Controller D_EXIM Read/Write Address 08H ...
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... Note : For the LAPD frame, the least significant two bits are the C/R bit and EA =0 bit suggested that the comparison with C/R bit be masked. EA=0 for two octet address frame e.g LAPD, EA=1 for one octet address frame. 8.1.13 D_ch SAPI1 Register D_SAP1 Value after reset: 00H SA17 SA16 SA15 SA14 W66910 PCI ISDN S/T-Controller D_RSTA Read D_SAM ...
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... This register contains the first choice of the second byte address of received frame. For LAPD frame, TA17 - TA11 is the TEI value, TA10 8.1.17 D_ch TEI2 Register D_TEI2 Value after reset: 00H W66910 PCI ISDN S/T-Controller Read/Write Address 0DH SA23 SA22 ...
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... D_RFIFO. These bits are valid only after an D_RME interrupt and remain valid until the frame is acknowledged via the RACK command. 8.1.20 Timer 2 TIMR2 Write Address 13H Value after reset : 00H TMD TIDLE TCN5 TCN4 W66910 PCI ISDN S/T-Controller TA23 TA22 TA21 TA20 D_RBCH Read Address 11H RBC11 RBC10 ...
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... When this bit is set to "1", a software reset signal is activated. The effects of this reset signal are equivalent to the hardware reset pin , except that it does not affect the 8-bit microprocessor interface circuit. Register can be read/written when SRST=1. This bit is not auto-clear, the software must write "0" to this bit to exit from the reset mode. W66910 PCI ISDN S/T-Controller 3 2 ...
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... Command/Indication Transmit Register Value after reset: 0FH CIR Read CODR3 CODR2 CODR1 CODR0 Code Descriptions 1111 Idle code on GCI interface 0111 U transceiver power up CIX Read/Write -54 - Data Sheet W66910 PCI ISDN S/T-Controller Address 58H/16H Address 17H Publication Release Date: Revision 1.0 Feb,2001 ...
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... Value after reset: 0FH CODX3 CODX2 CODX1 Code Descriptions 1000 Activate request command SQR Read SQX Read/Write -55 - Data Sheet W66910 PCI ISDN S/T-Controller 0 CODX0 Address 18H 0 S4 Address 19H Publication Release Date: and M bit A Feb,2001 Revision 1.0 ...
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... Pin IO3-2's output drivers are enabled bit positions in frames and 16 frame 1 and frame 6 etc. A PCTL Read/Write OE1 OE0 0 -56 - Data Sheet W66910 PCI ISDN S/T-Controller 0 Q4 Address 1AH 0 PXC Publication Release Date: Revision 1.0 Feb,2001 ...
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... Value after reset: 00H MO0R Read MO0X MO0I Read_clear MDR MER MDA -57 - Data Sheet W66910 PCI ISDN S/T-Controller Address 1BH 0 Read/Write Address 1CH 0 Address 1DH 0 0 MAB Publication Release Date: Revision 1.0 Feb,2001 ...
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... MR bit always 1. In addition, the MDR0 interrupt is blocked, except for the first byte of a packet (if MRIE0=1 internally controlled by the W66910 according to Monitor channel protocol. In addition, the MDR0 interrupt is enabled for all received bytes according to the Monitor channel protocol (if MRIE0=1). ...
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... Valid in GCI slave mode. SPU Software Power Up PD Power Down SPU After U transceiver power down, W66910 will receive the indication DC (Deactivation Confirmation) from GCI bus and then software has to set SPU HIGH. W66910 remains normal operation Setting SPU transceiver) to deliver GCI bus clocking ...
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... Monitor Receive Channel 1 Register Value after reset: FFH IO3 IO2 IO1 XDATA2 IO10 IO9 MO1R -60 - Data Sheet W66910 PCI ISDN S/T-Controller 0 IO0 Read/Write Address 3EH 0 IO8 Read Address 40H 0 Publication Release Date: Revision 1.0 Feb,2001 ...
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... MR bit always 1. In addition, the MDR1 interrupt is blocked, except for the first byte of a packet (if MRIE1=1 internally controlled by the W66910 according to Monitor channel protocol. In addition, the MDR1 interrupt is enabled for all received bytes according to the Monitor channel protocol (if MRIE1=1). ...
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... MXIE1 Monitor channel 1 Transmit Interrupt Enable Monitor interrupt status MDA1, MAB1 generation is enabled (1) or masked (0). MXC1 MX bit Control Determines the value of the MX bit always internally controlled by the W66910 according to Monitor channel protocol. 8.1.39 GCI IC1 Receive Register Value after reset: Undifined 7 6 ...
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... CI1R Read CI1R_4 CI1R_3 CI1R_2 CI1X CI1X_4 CI1X_3 CI1X_2 Read_clear MO0C IC1 IC2 -63 - Data Sheet W66910 PCI ISDN S/T-Controller 0 Address 48H 0 CI1R_1 Read/Write Address 49H 0 CI1X_1 Address 4AH 0 CI1 Publication Release Date: Feb,2001 Revision 1.0 ...
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... B1 channel address mask 1 B1 channel address mask 2 B1 channel address 1 B1 channel address 2 B1 channel receive frame byte count low B1 channel receive frame byte count high B1 channel transmit idle pattern -64 - Data Sheet W66910 PCI ISDN S/T-Controller 0 CI1 Publication Release Date: Revision 1.0 Feb,2001 ...
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... RA24 RA23 RBC6 RBC5 RBC4 RBC3 LOV RBC12 RBC11 IDLE6 IDLE5 IDLE4 IDLE3 Read Address 20H B1_XFIFO Write -65 - Data Sheet W66910 PCI ISDN S/T-Controller XME XRST FTS1 FTS0 XFR XDUN XFR XDUN XDOW XBZ MA12 MA11 MA10 MA22 MA21 ...
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... B1_ch HDLC controller. Zero bit insertion is performed on the data. This bit is also used in subsequent transmission of the frame. In extended transparent mode, settint this bit activates the transmission of B1_XFIFO data. No flag, CRC or zero bit insertion is added on the data. This bit is write-only. It's auto-clear. W66910 PCI ISDN S/T-Controller B1_CMDR Read/Write 3 2 ...
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... Note: The connection with microprocessor is through HDLC controller. When HDLC connects with layer 1, either transparent or extended transparent mode can be used. When HDLC connects with PCM port/GCI bus, only extended transparent mode can be used and the EPCM bit must be set to enable PCM function. SW56 Switch 56 Traffic W66910 PCI ISDN S/T-Controller Read/Write Address 23H 3 ...
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... XDUN Transmit Data Underrun This interrupt occurs when the B1_XFIFO has run out of data. In this case, the W66910 will automatically reset the transmitter and send the inter frame time fill pattern on B channel. The software must wait until transmit FIFO ready condition (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data ...
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... At least one byte of data has been overwritten in the B1_XFIFO. This bit is cleared only by XRST command. XBZ Transmitter Busy The B1_HDLC transmitter is busy when XBZ is read as "1". This bit may be polled. The XBZ bit is active when an XMS command was issued and the message has not been completely transmitted. W66910 PCI ISDN S/T-Controller Read/Write Address 25H 3 2 ...
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... MA11 MA10 B1_ADM2 Read/Write MA23 MA22 MA21 MA20 B1_ADR1 Read/Write RA13 RA12 RA11 RA10 B1_ADR2 Read/Write -70 - Data Sheet W66910 PCI ISDN S/T-Controller Address 27H Address 28H Address 29H Address 2AH Publication Release Date: Revision 1.0 Feb,2001 ...
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... B1_RFIFO is frame length modulus threshold. Remainder = RBC12-0 MOD threshold No of available data = remainder if remainder No of available data = threshold if remainder = 0 The remainder equals RBC5-0 if threshold is 64. 8.2.14 B1_ch Transmit Idle Pattern Value after reset: FFH W66910 PCI ISDN S/T-Controller RA23 RA22 RA21 RA20 B1_RBCL Read Address 2BH ...
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... B2_SW1 B2_SW0 SW56 RMR RME RDOV RMR RME RDOV RDOV CRCE RMB MA16 MA15 MA14 MA13 MA26 MA25 MA24 MA23 -72 - Data Sheet W66910 PCI ISDN S/T-Controller XMS XME XRST FTS1 FTS0 XFR XDUN XFR XDUN XDOW XBZ MA12 MA11 MA10 ...
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... +0 =5V, S/T layer 1 in state “F3 DDA Deactivated without clock” -73 - Data Sheet W66910 PCI ISDN S/T-Controller RA13 RA12 RA11 RA10 RA23 RA22 RA21 RA20 RBC3 RBC2 RBC1 RBC0 RBC11 RBC10 RBC9 RBC8 IDLE3 IDLE2 IDLE1 IDLE0 ...
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... External 50 oscillator XTAL1 signal or 51 N.C. XTAL2 Values Unit 7.680 MHz Max. 100 ppm Max Fundamental -74 - Data Sheet W66910 PCI ISDN S/T-Controller All pins except SX1,2, SR1,2 All pins except SX1,2, SR1,2 SX1,2 SX1,2 SX1,2 = Publication Release Date: Revision 1.0 Feb,2001 ...
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... Note 2 : The frequency of PBCK is 1536 kHz which includes 24 channels of 64 kbps data. The PFCK1 and PFCK2 are located at channel 1 and channel 2, each with PBCK duration. Detailed PCM timing ta1 ta2 PBCK ta3 PFCK1 PFCK2 ta4 PTXD ta7 W66910 PCI ISDN S/T-Controller 24 CHs Port1 Port1 ta5 ta6 -75 - Publication Release Date: Data Sheet Port2 Port2 Feb,2001 Revision 1 ...
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... Microprocessor Timing Intel mode read cycle timing t1 ALE t2 t3 A<7:0> AD<7:0> t6 CS# t4 RD# Min. Nominal Max. 325 195 325 455 t10 t9 D<7:0> t11 t5 -76 - Data Sheet W66910 PCI ISDN S/T-Controller Remarks Unit = ns A<7:0> Publication Release Date: Feb,2001 Revision 1.0 ...
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... Motorola mode read cycle timing A<7:0> t16 CS# t18 t20 DS# t22 RW t23 D<7:0> Motorola mode write cycle timing A<7:0> t16 CS# t18 t26 DS# t25 RW t29 t28 D<7:0> t10 t15 D<7:0> t7 t14 t13 t12 t17 t19 t21 t24 t17 t19 t27 -77 - Data Sheet W66910 PCI ISDN S/T-Controller A<7:0> Publication Release Date: Feb,2001 Revision 1.0 ...
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... Inputs are driven to 2.4 V for logical 1 and 0.4 V for logical 0. Measurements are made at 2.0 V for logical 1 and 0.8 V for logical 0. The AC testing input/output waveforms are shown below : 2.4 2.0 2.0 test point 0.8 0.8 0.4 W66910 PCI ISDN S/T-Controller Min. Max. Remarks 110 ...
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... ORDERING INFORMATION Part Number Package Type W66910CD 100 Pin LQFP W66910 PCI ISDN S/T-Controller Production Flow 0 0 Commercial +70 C -79 - Publication Release Date: Data Sheet Feb,2001 Revision 1.0 ...
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... H 0.626 0.634 0.630 15. 0.862 0.870 21.90 0.866 E L 0.030 0.018 0.024 0.45 L 0.039 1 y 0.003 -80 - Data Sheet W66910 PCI ISDN S/T-Controller Dimension in mm Nom Max 0.05 0.10 0.15 1.40 1.45 0.32 0.38 0.15 0.20 14.00 14.10 20.00 20.10 0.65 0.802 16.00 16.10 22.00 22.10 0.60 0.75 1.00 0. Publication Release Date: Feb,2001 Revision 1 ...
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... No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Note: All data and specifications are subject to change without notice. W66910 PCI ISDN S/T-Controller Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 ...