at572d940hf-cl ATMEL Corporation, at572d940hf-cl Datasheet

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at572d940hf-cl

Manufacturer Part Number
at572d940hf-cl
Description
Diopsis 940hf Arm926ej-s Plus Gflops
Manufacturer
ATMEL Corporation
Datasheet
Features
DIOPSIS
Core and a mAgicV VLIW DSP of the Magic DSP
Communication and Beam-forming Applications
High Performance MagicV VLIW DSP
ARM926EJ-S ARM Thumb Processor
Efficient ARM - DSP Interface through AHB master and slave ports, Memory Mapped
Registers and Ports, Interrupt Lines and Semaphores
Additional Embedded Memories
External Bus Interface (EBI)
USB
– 1 GFLOPS - 1.6 Gops at 100 MHz
– AHB Master Port, integrated DMA Engine and AHB Slave Port
– Up to 10 Arithmetic Operations per Cycle (4 Multiply, 2 Add/subtract, 1 Add, 1
– Native Support for Complex Arithmetic and Vectorial SIMD Operations: One
– 32-bit Integer and IEEE
– 16-port Data Register File: 256 Registers Organized in Two 128-register Banks
– 5-issue predicated VLIW Architecture with Orthogonal ISA, Code Compression
– 6 Accesses per Cycle Data Memory System (4 Accesses per Cycle for VLIW
– 2 Independent Address Generation Units Operating on a 64 Registers Address
– 1.7 Mbits of On-chip SRAM:
– 16 K x 40-bit Data Memory Locations (6 Memory Accesses per Cycle)
– 8 K x 128-bit Dual Port Program Memory Location, Equivalent to ~50K DSP
– DMA Access to the External Program and Data Memory
– Three Main Operating Modes: Run, Debug and Sleep Modes
– User Mode and Privileged Interrupt Service Mode
– Efficient Optimizing Assembler and C-Oriented Architecture: Allows Easy
– DSP instruction extensions
– ARM Jazelle
– 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
– 220MIPS at 200MHz
– Memory Management Unit
– EmbeddedICE
– 32-KByte of internal ROM, two-cycle access at maximum bus speed
– 48-KByte of internal SRAM, single-cycle access at maximum processor or bus
– Supports SDRAM, Static Memory, SmartMedia
– USB 2.0 Full Speed (12 Mbits per second) Host Double Port
Subtract 40-bit Floating Point and 32-bit Integer) Allowing Single Cycle FFT
Butterfly
Complex Multiply with Dual Add/sub per Clock Cycle or Two Real Multiply and Two
Add/sub or Simple Scalar Operations
and Hardware Support for Code Efficient Software Pipeline Loops
Operations + 2 Accesses per Cycle for DMA Transfers) supported by Flexible
Addressing Capability
Register File Supporting Complex or Micro-Vectorial Accesses, and DSP features:
Programmable Stride and Circular Buffers
Assembler Instructions (typical) thanks to Code Compression and SW Pipelining
Exploitation of the Available Hardware Parallelism
speed
®
Dual Core System Integrating an ARM926EJ-S
®
Technology for Java
In-circuit Emulation, Debug Communication Channel Support
®
40-bit Extended Precision Floating Point Numeric Format
®
Acceleration
family, optimized for Audio,
®
and NAND Flash, CompactFlash
ARM
®
Thumb
®
Processor
®
DIOPSIS 940HF
ARM926EJ-S PLUS
ONE GFLOPS DSP
AT572D940HF
Preliminary
Summary
NOTE: This is a summary document.
The complete document is available
under NDA. For more information,
please contact your local Atmel sales
office.
7010AS–DSP–07/07

Related parts for at572d940hf-cl

at572d940hf-cl Summary of contents

Page 1

... Audio, ® Acceleration ® and NAND Flash, CompactFlash Processor DIOPSIS 940HF ARM926EJ-S PLUS ONE GFLOPS DSP AT572D940HF Preliminary Summary NOTE: This is a summary document. The complete document is available under NDA. For more information, please contact your local Atmel sales office. ® ...

Page 2

... Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • Two Two-Wire Interfaces (TWI) – Master Mode Support, All Two-wire Atmel EEPROM’s Supported • Two CAN Interfaces – Fully compliant with CAN 2.0 Part A and 2.0 Part B AT572D940HF Preliminary 2 ® Infrared Modulation/Demodulation 7010AS–DSP–07/07 ...

Page 3

... Automatic Protocol Control and Fast Automatic Data Transfers with PDMA, MMC and SDCard Compliant • IEEE 1149.1 JTAG Boundary Scan on All Digital Pins • Required Power Supplies: – 1.1V / 1.2V for VDDCORE and VDDOSC – 3.3V for VDDPLLA – 3.3V for VDDIOP (Peripheral I/Os) and for VDDIOM (Memory I/Os) • Available in 324-ball CABGA Package 7010AS–DSP–07/07 AT572D940HF Preliminary 3 ...

Page 4

... A rich set of peripherals and a 48 Kbytes internal memory provide a highly flexible and inte- grated system solution. The ARM926EJ-S supports the Jazelle technology for Java acceleration. AT572D940HF Preliminary 4 ™ RISC controller with the very high performance of the DSP. 7010AS–DSP–07/07 ...

Page 5

... Ball Configuration Table 2-1. AT572D940HF Ball Assignment (I/O: 191 balls) Name Pin Name A0/NBS0 B2 D5 A1/NBS2/NWR2 D10 A6 E4 D11 A7 E3 D12 A8 F6 D13 A9 G6 D14 A10 F3 D15 A11 H8 D16 A12 F2 D17 A13 F1 D18 A14 G3 D19 A15 H7 D20 ...

Page 6

... PIOC5 G12 PIOC19 PIOC6 F12 PIOC20 PIOC7 G13 PIOC21 PIOC8 F18 PIOC22 PIOC9 M18 PIOC23 PIOC10 L12 PIOC24 Table 2-2. AT572D940HF Ball Assignment (Power and Ground: 127 balls) Name Pin Name VDDCORE F4 VDDIOM VDDCORE J4 VDDIOM VDDCORE L6 VDDIOM VDDCORE T2 VDDIOM VDDCORE M9 VDDIOM VDDCORE ...

Page 7

... Table 2-2. AT572D940HF Ball Assignment (Power and Ground: 127 balls) (Continued) Name Pin Name GND U10 GND GND V11 GND GND R11 GND GND V12 GND GND R13 GND GND U14 GND GND U16 GND GND P15 GND GND P18 GND GND ...

Page 8

... EBI D0- D31 Data Bus EBI NWAIT External Wait Signal EBI BMS Boot Memory Select ETH E_RXER Ethernet RMII Receive Error AT572D940HF Preliminary 8 Active Type Level Notes bi-03 input through PIO line bi-03 output through PIO line bi-03 output through PIO line internal pull-down resistor (ARM JTAG ...

Page 9

... Slow Clock Oscillator Enable PIOA0 - PIO A Parallel Input/Output A PIOA31 PIOB0 - PIO B Parallel Input/Output B PIOB31 PIOC0 - PIO C Parallel Input/Output C PIOC31 PLL PLL_RCA PLL A Filter PLL PLL_RCB PLL B Filter PMC A_CK ARM Clock 7010AS–DSP–07/07 AT572D940HF Preliminary (Continued) Active Type Level bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 high bi-03 bi-03 bi-03 bi-03 bi- out- ...

Page 10

... SPI 0 Master Out/Slave In data SPI SPI0_MISO SPI 0 Master In/Slave Out data SPI SPI0_NCS0 SPI 0 Input/Output Chip select SPI0_NCS1 - SPI SPI 0 Output Chip Selects SPI0_NCS3 SPI SPI0_CK SPI 0 Serial clock AT572D940HF Preliminary 10 (Continued) Active Type Level bi-03 bi-03 out-03 out-04 high out-03 low out-03 ...

Page 11

... Synchronous Serial Controller 1 SSC SSC1_TK Transmit Bit Clock Synchronous Serial Controller 1 SSC SSC1_RK Receive Bit Clock Synchronous Serial Controller 2 SSC SSC2_TXD Data Out Synchronous Serial Controller 2 SSC SSC2_TF Transmit Frame Clock 7010AS–DSP–07/07 AT572D940HF Preliminary (Continued) Active Type Level bi-03 bi-03 out-03 low bi-03 low bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 ...

Page 12

... Two Wire 0 Data TWI TW0_CK Two Wire 0 Clock TWI TW1_D Two Wire 1 Data TWI TW1_CK Two Wire 1 Clock USBD USBD_DM USB Device Port Data - USBD USBD_DP USB Device Port Data + USBH USBHA_DM USB Host Port A Data - AT572D940HF Preliminary 12 (Continued) Active Type Level bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 low bi-03 ...

Page 13

... Main Oscillator PLLB Power Supply Power VDDPLLA PLLA power supply Ground GND Core and IO Ground 32KHz Oscillator Ground Ground GNDOSC32 Main Oscillator PLLB Ground Ground GNDOSCM Ground GNDPLLA PLLA Ground 7010AS–DSP–07/07 AT572D940HF Preliminary (Continued) Active Type Level usb-bi usb-bi usb-bi bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 ...

Page 14

... SPIx_NCS0 SPIx_NCS1-SPIx_NCS3 SPIx_CK PIO A-B-C Controllers TWx_CK TWx_D SSCx_RXD SSCx_TXD SSCx_TF SSC 0-1-2-3 SSCx_TK SSCx_RF SSCx_RK MCCK MCCDA MCDA0-MCDA3 CANx_RX CANx_TX AT572D940HF Preliminary 14 ARM926EJ-S ARM926EJ-S ICE ICE Instruction Cache Instruction Cache MMU MMU 16K bytes 16K bytes TCM IF TCM IF SYSC RST CNTL ...

Page 15

... USB Host 5. Ethernet MAC 10/100 6. mAgicV JTAG and of five slaves: 0. ARM926 SRAM 1. ARM926 ROM 2. mAgicV Registers and Memories + USB Host Registers 3. The External Bus Interface 4. The AHB-APB bridge 7010AS–DSP–07/07 AT572D940HF Preliminary ™ bus: the multilayer AHB matrix and the APB. 15 ...

Page 16

... Both the odd and even sides of the register file are 9-ported (4-read ports and 4-write ports for computing/move opera- tions + 1 port for independent debug access), making a total of 16 I/O ports available for the data AT572D940HF Preliminary 16 mAgicV DSP Block Diagram ...

Page 17

... Registers named A0-A15 are used for the storage of pointers, while registers M0-M15 are for the 16-bit integer modifiers. For circular buffers, S0-S15 store the Start Addresses of the buffers, and L0-L15 are initialized with the circular buffer lengths. The MAGU 7010AS–DSP–07/07 AT572D940HF Preliminary 17 ...

Page 18

... DSP libraries, the density is even greater where software pipelining is activated. If the on-chip program memory is not large enough to contain the full DSP application, a DMA must be launched to refill the dual-port Program Memory. Thanks to the program compression, the pro- gram memory refill does not stall the activities of the DSP core. AT572D940HF Preliminary 18 7010AS–DSP–07/07 ...

Page 19

... Debug Mode can be used for initialization and also for debugging purposes. By accessing the Command Register, the ARM can change the operating status of the DSP (Run/System Mode), 7010AS–DSP–07/07 Section 5.3.15.1 and Section 5.3.15.2 AT572D940HF Preliminary Section 5.3.15.3 below). At every cycle, one port of the Data below) all 19 ...

Page 20

... During Run mode, mAgicV can execute either in User mode or in Privileged Interrupt Mode. 5.3.17 ARM<->mAgicV Interrupts In order to allow a tight coupling between the operations of mAgicV and the ARM at run time, they can exchange synchronization signals, based on interrupts. AT572D940HF Preliminary 20 7010AS–DSP–07/07 ...

Page 21

... If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface. 7010AS–DSP–07/07 AT572D940HF Preliminary ™ family of general purpose microprocessors. The ARM926 Table 5-1 to Table 5-4 ...

Page 22

... The USB host acting as an AHB master controls the data exchange between the two USB host channels (port A and port B) and the ARM Internal RAM or the external memories. The USB Host Port features: AT572D940HF Preliminary 22 Activates a Boot uploader enabling small monitor functionalities (read/write/run) ™ ...

Page 23

... Address Bus (four msb via PIO lines) • 32-bit Data Bus • Multiple Access Modes supported • Byte Write Lines • Programmable Wait State Generation • Programmable Data Float Time • Slow clock mode supported 7010AS–DSP–07/07 AT572D940HF Preliminary 23 ...

Page 24

... Address Size (MB) mst # 0 0x0000 0000 256 0x1000 0000 8 x 256 0x9000 0000 6 x 256 0xF000 0000 256 AT572D940HF Preliminary 24 shows the D940HF global memory map: ARM9-D PDC mst #1 mst # 2 Internal Memories (See External Memories (See Undefined (Abort) Table 5-4 Internal Peripherals (See ...

Page 25

... ARM9-D mst # 1 REMAP=1 REMAP=0 BMS=1 BMS=0 EBI EBI IntRAM C IntROM NCS0 ARM AHB MEM IntROM USB cfg magicV AT572D940HF Preliminary masters magicV USB ETH mst #3 mst #4 mst #5 EBI CS0: EBI CS2: SMC EBI CS6: SMC EBI CS7: SMC magic PDC V ...

Page 26

... F400 512 0xFFFF F600 512 0xFFFF F800 512 0xFFFF FA00 512 0xFFFF FC00 256 0xFFFF FD00 256 0xFFFF FE00 2 x 256 AT572D940HF Preliminary 26 masters ARM9-D PDC magicV reserved USB DEV MCI TWI-0 USART-0 USART-1 USART-2 SSC-0 SSC-1 ...

Page 27

... USB Device AT572D940HF Preliminary Host Clock Assignment PIO A PIO B PIO C ETH APB ETH AHB USART-0 USART-1 USART-2 MCI TWI-0 SPI-0 SPI-1 SSC-0 SSC-1 SSC-2 TIMER-0 TIMER-1 TIMER-2 USB HOST SSC-3 TW1 ...

Page 28

... PIO A [17] ETH input: ECRSDV PIO A [18] ETH input: ERX0 PIO A [19] ETH input: ERX1 PIO A [20] ETH input: ERXER PIO A [21] PIO A [22] AT572D940HF Preliminary 28 Peripheral ID (Continued) Peripheral ID Peripheral Clock Assignment Periph OUTPUT A SPI 0 output: CS1 SPI 0 output: CS2 ...

Page 29

... SSC: TD2 SSC: TF2 SSC: TK2 SSC: RF2 SSC: RK2 SSC: TD3 SSC: TF3 SSC: TK3 AT572D940HF Preliminary Periph INPUT B Periph OUTPUT B mAgicV output: M_SIRQ0 (III) mAgicV output: M_SIRQ1 (III) USART 2 output: RTS (III) TIMER bidir: TIMER_OUT A2 PMC output: CKOUT 2 EBI output: SMOE ...

Page 30

... PIO C [14] USART 2 RXD PIO C [15] USART 2 TXD PIO C [16] USART 2 CTS PIO C [17] PIO C [18] USART 2 SCK PIO C [19] TIMER bidir: TIMER_OUT B2 AT572D940HF Preliminary 30 Periph OUTPUT A SSC: RF3 SSC: RK3 CAN 0: dout EBI: A[22] EBI: A[23] EBI: A[24] EBI: A[25]-CFRNW Periph OUTPUT A SPI 1 output: CS1 ...

Page 31

... Controls the interrupt lines (nIRQ and nFIQ) of ARM926 • Thirty-two individually maskable and vectored interrupt sources • Programmable Edge-triggered or Level-sensitive Internal Sources • Programmable Positive/Negative Edge-triggered or High/Low Level sensitive 7010AS–DSP–07/07 AT572D940HF Preliminary Periph OUTPUT A Periph INPUT B CAN 1: dout DBGU output: DTXD ...

Page 32

... Pulse Width Modulation • Up/down Capabilities Each channel is user-configurable and contains: • Three external clock inputs • Five internal clock inputs • Two multi-purpose input/output signals 5.11.9 Two Wire Interface (TWI) The D940HF provides two independent TWIs. AT572D940HF Preliminary 32 7010AS–DSP–07/07 ...

Page 33

... The Debug Unit also generates the Debug Communication Channel (DCC) signals provided by the In-circuit Emulator of the ARM processor visible to the software. These signals indicate the status of the DCC read and write registers and generate an interrupt to the ARM processor, allowing the handling of the DCC under interrupt control. 7010AS–DSP–07/07 AT572D940HF Preliminary 33 ...

Page 34

... The MCI has two slots, each supporting: – One slot for one MultiMedia Card bus ( cards) or – One SD Memory Card The PDC connection allows direct data transfer between these serial devices and mAgicV data memory, ARM internal memory or the external memories. AT572D940HF Preliminary 34 7010AS–DSP–07/07 ...

Page 35

... Mechanical Drawing Figure 6-1. 324-ball CABGA Package Drawing (dimensions in mm) 7010AS–DSP–07/07 AT572D940HF Preliminary 35 ...

Page 36

... VDDPLLA pins, which power the PLLA cell (3.3V) 7.1 Power Consumption The D940HF consumes about 2mA in typical conditions of static current VDDCORE. For dynamic power consumption the D940HF consumes about 300mA in typical conditions at maximum working frequencies with a 20% toggling rate. AT572D940HF Preliminary 36 7010AS–DSP–07/07 ...

Page 37

... Table 8-1. Ordering Information Part Number Temp. Range AT572D940HF 0°C to 70°C AT572D940HF-CL 0°C to 70°C AT572D940HF-CJ -40°C to 85°C 1. Some peripherals are not accessible by the user in this low-cost version. Reduced Peripheral Set = Full Peripheral Set - 2 CANs -3 SSCs - 1 SPI - 1 TWI - 2 USARTs. Consequently the related PIO lines can be used only as SW controlled PIO lines (not linked to any peripherals). 7010AS– ...

Page 38

... Revision History Doc. Rev. Date 7010AS 07/07 AT572D940HF Preliminary 38 Comments • Initial document release 7010AS–DSP–07/07 ...

Page 39

... Atmel Corporation. All rights reserved. Atmel ™ trademarks, Magic DSP and others are trademarks of Atmel Corporation or its subsidiaries. ARM trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others. International Atmel Asia ...

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