s5935qrc Applied Micro Circuits Corporation (AMCC), s5935qrc Datasheet - Page 131
s5935qrc
Manufacturer Part Number
s5935qrc
Description
Pci Product
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
1.S5935QRC.pdf
(204 pages)
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S5935 – PCI Product
Once interrupts are enabled, the interrupt service routine must access the mailboxes and clear the interrupt
source. A particular application may not require all of the steps shown. For instance, a design may only use incom-
ing mailbox interrupts and not require support for outgoing mailbox interrupts. The interrupt service routine tasks
are shown below:
AMCC Confidential and Proprietary
Enabling Add-On mailbox interrupts:
With either the Add-On or PCI interface, these two steps can be performed with a single access to the appropriate register.
They are shown separately here for clarity.
Servicing a PCI mailbox interrupt (INTA#):
1. Enable Add-On outgoing mailbox interrupts. A specific byte within one of the outgoing mailboxes is identified to assert
2. Enable Add-On incoming mailbox interrupts. A specific byte within one of the incoming mailboxes is identified to assert
1. Identify the interrupt source(s). Multiple interrupt sources are available on the S5935. The interrupt service routine must
2. Check mailbox status. The mailbox status bits indicate which mailbox bytes must be read or written.
3. Access the mailbox. Based on the contents of MBEF, mailboxes are read or written. Reading an incoming mailbox byte
4. Clear the interrupt source. The PCI INTA# signal is deasserted by clearing the interrupt request. The request is cleared
INTCSR
INTCSR
INTCSR
INTCSR
MBEF
MBEF
OMBx
AINT
AINT
AINT
AINT
AINT
AINT
IMBx
IRQ# when read by the PCI interface.
IRQ# when written by the PCI interface.
verify that a mailbox generated the interrupt (and not some other interrupt source).
clears the corresponding status bit in MBEF.
by writing a ‘1’ to the appropriate bit.
Bit 12
Bits 11:10
Bits 9:8
Bit 4
Bits 3:2
Bits 1:0
Bit 16
Bit 17
Bits 31:16
Bits 15:0
Bits 31:0
Bits 31:0
Bit 16
Bit 17
Enable outgoing mailbox interrupts
Identify mailbox to generate interrupt
Identify mailbox byte to generate interrupt
Enable incoming mailbox interrupts
Identify mailbox to generate interrupt
Identify mailbox byte to generate interrupt
PCI outgoing mailbox interrupt indicator
PCI incoming mailbox interrupt indicator
Full PCI incoming mailbox bytes
Empty PCI outgoing mailbox bytes
PCI outgoing mailboxes
PCI incoming mailboxes
Clear PCI outgoing mailbox interrupt
Clear PCI incoming mailbox interrupt
Revision 1.02 – June 27, 2006
Data Book
DS1527
131
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